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An Overview of Monolithic Fabrication Processes and Structures
Monolithic integrated-circuit fabrication can be illustrated by studying the basic cross sections of MOS and bipolar transistors. The n-channel MOS transistor is formed in a p-type substrate. Source/drain regions are formed by selectively converting shallow regions at the surface to n-type material. Thin and thick silicon dioxide regions on the surface form the gate insulator of the transistor and server to isolate one device from another. A thin film of polysilicon is used to form the gate of the transistor, and aluminum is used to make contact to the source and drain. Interconnections between devices can be made using the diffusions and the layers of polysilicon and metal.
The bipolar transistor has alternate n- and p-type regions selectively fabricated on a p-type substrate. Silicon dioxide is again used as an insulator, and a metal such as aluminum is used to make electrical contact to the emitter, base, and collector of the transistor.
These structures are fabricated through the repeated application of a number of basic processing steps:
Shallow n- and p-type layers are formed by high-temperature (1000 to 1200 degrees C) diffusion of donor or acceptor impurities into silicon or by ion implantation, in which the wafer is bombarded with high-energy donor or acceptor atoms generated in a high-voltage particle accelerator.
In order to build devices and circuits, the n- and p-type regions must be formed selectively in the surface of the wafer. Silicon dioxide, silicon nitride, polysilicon, and other materials can all be used to mask areas of the wafer surface to prevent penetration of impurities during ion implantation or diffusion. Windows are cut in the masking material by etching with acids or in a plasma. Window patterns are transferred to the wafer surface from a mask through the use of optical techniques. The masks are also produced using photographic reduction techniques.
Photolithography includes the overall process of mask fabrication as well as the process of transferring patterns from the masks to the surface of the wafer. The photolithographic process is critical to the production of integrated circuits, and the number of mask steps is often used as a measure of complexity when comparing fabrication processes.
Metal-Oxide-Semiconductor (MOS) Processes
Basic NMOS Process
The starting wafer is first oxidized to form a thin-pad oxide layer
of silicon dioxide (SiO2) which protects the silicon surface.
Silicon nitride is then deposited by a low-pressure chemical vapor deposition
(LPCVD) process. Mask #1 defines the active transistor areas. The nitride/oxide
sandwich is etched away everywhere except where transistors are to be formed.
A boron implantation is performed and followed by an oxidation step. The
nitride servers as both an implantation mask and an oxidation mask. After
the nitride and thin oxide padding layers are removed, a new thin layer
of oxide is grown to server as the gate oxide for the MOS transistors.
Following gate-oxide growth, a boron implantation is commonly used to adjust
the threshold voltage to the desired value.
Polysilicon is deposited over the complete wafer using a CVD process. The second mask defines the polysilicon gate region of the transistors. Polysilicon is etched away everywhere except over the gate regions and the areas used for interconnection. Next, the source/drain regions are implanted through the thin oxide regions. The implanted impurity may be driven in deeper with a high-temperature diffusion step. More oxide is deposited on the surface, and contact openings are defined by the third mask step. Metal is deposited over the wafer surface by evaporation or sputtering. The fourth mask step is used to define the interconnection pattern which will be etched in the metal. A passivation layer of phosphosilicate glass is deposited on the wafer surface, and the final mask (#5) is used to define windows so that bonding wires can be attached to pads on the periphery of the IC die.
This simple process requires five mask steps. Note that these masks steps use subtractive processes. The entire surface of the wafer is first coated with a desired material, and then most of the material is removed by wet chemical or plasma etching.
Basic Complementary MOS (CMOS) Process
One new mask, beyond that of the NMOS process, is used to define the
"p-well" or "p-tub," which serves as the substrate for the
n-channel devices. A second new mask step is used to define the
source/drain regions of the p-channel transistors. Additional masks
may be used to adjust the threshold voltage of the MOS transistors and
are very common in state-of-the-art NMOS and CMOS processes.
Some recent CMOS processes use an n-well instead of a p-well. The n-well can be added to an existing NMOS process with a minimum of change, and it permits high-performance NMOS and CMOS on the same chip. Twin-well processes have also been developed recently. Both a p-well and an n-well are formed in a lightly doped substrate, and the n- and p-channel devices can each be optimized for highest performance. Twin-well very large-scale integration (VLSI) processes use lightly doped layers grown on heavily doped substrates to suppress a CMOS failure mode called latchup.
Basic Bipolar Processing
Basic bipolar fabrication is somewhat more complex than single-channel MOS processing. A p-type silicon wafer is oxidized, and the first mask is used to define a diffused region called the buried layer or subcollector. This diffusion is used to reduce the collector resistance of the bipolar transistor. Following the buried-layer diffusion, a process called epitaxy is used to grow single-crystal n-type silicon on top of the silicon wafer. The epitaxial growth process results in a high-quality silicon layer with the same crystal structure as the original silicon wafer. An oxide layer is then grown on the wafer. Mask two is used to open windows for a deep p-diffusion, which is used to isolate one bipolar transistor from another. Another oxidation follows the isolation diffusion. Mask three opens windows in the oxide for the p-type base diffusion. The wafer is usually oxidized during the base diffusion, and mask fouris used to open windows for the emitter diffusion. The same diffusion step places an n+ region under the collector contact to ensure that a good ohmic contact will be formed during subsequent metallization. Masks five, six, and seven are used to open contact windows, pattern the metallization layer, and open windows in the passivation layer just as in the NMOS process. Thus the basic bipolar process requires seven mask levels compared with five for the basic NMOS process.
After the MOS or bipolar porocess is completed, each die on the wafer is tested, and bad dice are marked with ink. The wafer is then sawed apart. Good dice are mounted in various packages for final testing and subsequent sale or use.