Process Sequence Stuff (part #3)

Gate oxide thickness - The gate oxide will generally be made as thin as possible, commensurate oxide breakdown and reliability considerations.

Breakdown of SiO₂ = 5-10 MV/cm
i.e. 50 to 100V across 100nm
< 10nm not practical

Substrate Doping and Threshold Voltage

ç F _F ê = (kT/q)ln(N_B/n_i)
N_B - substrate doping
F _M - c = -0.11 for Al gate
F _M - c = 0 for n+ doped polysilicon gate
F _M - c = +1.12 for p+ doped polysilicon gate
Q_tot = total oxide and interface charge per cm²
V_BS = source-to-drain substrate voltage
C_o = (K_s Î _o)/x_o oxide capacitance per unit area

Always check breakdown as a result of one-side pn junction action between channel and drain and channel and source. Also, always check the punch-through.

The above equations come from the one-side step junction approximation.

V_A = applied voltage
F _bi = built-in voltage

channel length > 2W, punch-through should not occur.

The capacitance associated with this diffused junction is given by

C_j = (K_s Î _o)/W per unit area

Remember the larger the doping, the larger the capacitance. V_SB the source-to-substrate voltage also depends on substrate doping.

(substrate doping ­ ® V_SB ­ ® V_T­ ). Tradeoffs involve:
substrate doping ­ ® V_T­
substrate doping ­ ® C_j­ ® V_breakdown ¯ ® m _M¯
 
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