In this section, we will discuss in detail the fabrication procedure for MOS process design. We will examine the importance of channel-length control; layout ground rules and ground-rule design; source/drain breakdown and punch -through voltages; and threshold-voltage adjustment. Metal gate, self-aligned silicon gate, and poly-silicon gate technologies will be examined.

Cross section of two adjacent NMOS transistors

In the linear region of operation

where V_GS = V_T
V_DS = V_GS - V_T
C_o = K_S Î _o/X_o oxide capacitance per unit area
m _n = average majority - carrier mobility
V_T = threshold voltage

Specifications for MOS Device Design

1. circuit-power-supply voltages (set V_DS & V_GS)
2. width and length of transistor
3. process sequence times, temperature, etc.

• gate-oxide thickness
• field-oxide thickness
• substrate doping
• field and threshold adjustments implantation

1. set of design-rules or ground-rules

• minimum channel length and width
• spacing between features
• overlaps between features
• mask alignment sequence and tolerances