Homework Assignment 4

Chapter 3

1.

(Hazard-free design )

 a.

Determine the Boolean expression found by removing the static one hazards from the following expression.

 b.

Draw the logic diagram for your static one hazard-free expression in part a .

2.

(NAND-NAND Mappings) Draw schematics for the following expressions, mapped into NAND-only networks. You may assume that literals and their complements are available.

 a.

 b.

3.

(NOR-NOR Mappings) Draw schematics for the following expressions, mapped into NOR-only networks. You may assume that literals and their complements are available.

 a.

 b.

4.

Multilevel Logic

  

Figure:

 a.

Write down the function represented by the circuit in Fig. 1 in a multilevel factored form using AND, OR, and NOT operations only.

 b.

Derive the minimal Boolean expression (minimum number of literals and fewest number of gates) for the function represented above.

5.

(Multilevel Synthesis ) Design a multiple output logic network whose input is a BCD digit and whose outputs are defined as follows: f₁: Detects input digits that are divisble by four, f₂: Detects numbers greater than or equal to 3, f₃: Detects numbers less than 7.

You must turn in

 a.

The truth table and the minimal SOP form for the function obtained using KMaps.

 b.

The circuit diagram/schematic representing the two level Boolean expressions obtained in a.

 c.

Use factoring, decomposition, substitution, etc. to obtain a multilevel circuit that uses 2-input gates and inverters only. Draw the multilevel circuit diagram. If possible, share gates across different outputs. Hence, fewer gates will be required to build the complete circuit. If you have trouble, run espresso and see if different outputs use the same implicants.