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-- Copyright 2001 by Howard University All rights reserved.
--
-- Design:	FunCore 
-- Name: Generated by FunCoreGen program (Clay Gloster - author)
--	
-- Date:		October 2001
-- Description:  PLEASE EDIT 
-- 			
--			
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Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
ENTITY MultAcc IS
	PORT(
	Clk,Reset: IN std_logic;
	ENABLE : IN std_logic;
	EMPTY : IN std_logic;
	A : IN std_logic_vector (31 downto 0);
	B : IN std_logic_vector (31 downto 0);
	Q : OUT std_logic_vector (31 downto 0);
	DONE : OUT std_logic;
);
END MultAcc;
ARCHITECTURE STRUCTURAL OF MultAcc IS
COMPONENT FpMultCore_8
PORT(
	clk		: IN std_logic;
	reset	: IN std_logic;
	EnR		: IN std_logic;
	EnL		: IN std_logic;
	Op_A		: IN std_logic_vector(31 DOWNTO 0);
	Op_B		: IN std_logic_vector(31 DOWNTO 0);
	Op_Q		: OUT std_logic_vector(31 DOWNTO 0);
	EnN		: OUT std_logic);
END COMPONENT;
COMPONENT acc_core
PORT(
	clk		: IN std_logic;
	reset	: IN std_logic;
	Enable,Empty		: IN std_logic;
	Op_A		: IN std_logic_vector(31 DOWNTO 0);
	Op_Q		: OUT std_logic_vector(31 DOWNTO 0);
	Done		: OUT std_logic);
END COMPONENT;
SIGNAL SIG0 : std_logic_vector(31 downto 0);
SIGNAL BSIG0 : std_logic;
BEGIN
I0:	FpMultCore_8 PORT MAP (clk,reset,ENABLE,ENABLE,A,B,SIG0,BSIG0);
I1:	acc_core PORT MAP (clk,reset,BSIG0,EMPTY,SIG0,Q,DONE);
END STRUCTURAL;