--------------------------------------------------------------
-- Copyright 1999 by NC State University All rights reserved.
--
-- Design:	1 bit full adder
-- Name:		Ibrahim Sahin
--	
-- Date:		March 2000
-- Description:
-- Pipelined.
--------------------------------------------------------------
Library IEEE;  
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--use WORK.all;
ENTITY full_adder IS
	PORT(a	: IN std_logic;
		b	: IN std_logic;
		cin	: IN std_logic;
		s	: OUT std_logic;
		cout	: OUT std_logic);
END full_adder;
ARCHITECTURE full_adder_a OF full_adder IS
BEGIN
	PROCESS(a,b,cin)
	BEGIN
		s	<= a XOR b XOR cin;
		cout	<= (a AND b) OR (a AND cin) OR (b AND cin);
	END PROCESS;
END full_adder_a;
--------------------------------------------------------------
-- Copyright 2000 by NC State University All rights reserved.
--
-- Design: 9 bit register
-- Name:    Ibrahim Sahin
--	
-- Date:    April 2000
-- Description:
--  Pipelined.
--------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_Logic_1164.all;
ENTITY reg_g IS
	GENERIC(width : integer:= 4);
	PORT(Clk		: IN std_logic;
		Reset	: IN std_logic;
		Run		: IN std_logic;
		Datain	: IN std_logic_vector(width-1 DOWNTO 0);
		Q		: OUT std_logic_vector(width-1 DOWNTO 0));
END reg_g;
ARCHITECTURE RTL OF reg_g IS
	SIGNAL D : std_logic_vector(width-1 DOWNTO 0);
BEGIN
	PROCESS
	BEGIN
		WAIT UNTIL ((Clk'EVENT) AND (Clk= '1'));
		IF (Reset = '1') THEN 		 -- Changed Reset to Active High
			f1 : FOR i IN width-1 DOWNTO 0 LOOP
					D(i) <= '0';
				END LOOP;
		ELSE
			IF (Run = '1') THEN
				D <= Datain;
			ELSE
				D <= D;
			END IF;
		END IF ;
	END process;
	Q <= D;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by NC State University All rights reserved.
--
-- Design:	GENERIC Pipeline slice OF the multpilier
-- Name:		Ibrahim Sahin
--	
-- Date:		March 2000
-- Description:
-- Pipelined.
--------------------------------------------------------------
Library IEEE;  
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--use WORK.all;
ENTITY OneSlice IS
	PORT(InA		: IN std_logic_vector(23 DOWNTO 0);
		InB		: IN std_logic;
		SumIn	: IN std_logic_vector(23 DOWNTO 0);
		CarryIn	: IN std_logic_vector(23 DOWNTO 0);
		SumOut	: OUT std_logic_vector(23 DOWNTO 1);
		CarryOut	: OUT std_logic_vector(23 DOWNTO 0));
END OneSlice;
ARCHITECTURE behv OF OneSlice IS
	SIGNAL AB : std_logic_vector(23 DOWNTO 0);
BEGIN
	loop1:FOR i IN 23 DOWNTO 0 GENERATE
			AB(i) <= InA(i) and InB;
		END GENERATE;
	loop2:FOR i IN 23 DOWNTO 1 GENERATE
		SumOut(i)	<= AB(i) xor SumIn(i) xor CarryIn(i);
		CarryOut(i) <= (AB(i) and SumIn(i)) or (AB(i) and CarryIn(i)) or (SumIn(i) and CarryIn(i));
	END GENERATE;
	CarryOut(0) <= (AB(0) and SumIn(0)) or (AB(0) and CarryIn(0)) or (SumIn(0) and CarryIn(0));
END behv;
--------------------------------------------------------------
-- Copyright 1999 by NC State University All rights reserved.
--
-- Design:	GENERIC Pipeline Block OF the multiplier
-- Name:		Ibrahim Sahin
--	
-- Date:		March 2000
-- Description:
-- Pipelined.
--------------------------------------------------------------
Library IEEE;  
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--use WORK.all;
ENTITY OneBlock IS
	PORT(InA		: IN std_logic_vector(23 DOWNTO 0);
		InB		: IN std_logic_vector(3 DOWNTO 0);
		SumIn	: IN std_logic_vector(23 DOWNTO 0);
		CarryIn	: IN std_logic_vector(23 DOWNTO 0);
		SumOut	: OUT std_logic_vector(22 DOWNTO 0);
		CarryOut	: OUT std_logic_vector(23 DOWNTO 0));
END OneBlock;
ARCHITECTURE behv OF OneBlock IS
	COMPONENT OneSlice
		PORT(InA		: IN std_logic_vector(23 DOWNTO 0);
			InB		: IN std_logic;
			SumIn	: IN std_logic_vector(23 DOWNTO 0);
			CarryIn	: IN std_logic_vector(23 DOWNTO 0);
			SumOut	: OUT std_logic_vector(23 DOWNTO 1);
			CarryOut	: OUT std_logic_vector(23 DOWNTO 0));
	END COMPONENT;
	SIGNAL S12 : std_logic_vector(23 DOWNTO 1);
	SIGNAL S1_2: std_logic_vector(23 DOWNTO 0);
	SIGNAL C12 : std_logic_vector(23 DOWNTO 0);
	SIGNAL S23 : std_logic_vector(23 DOWNTO 1);
	SIGNAL S2_3: std_logic_vector(23 DOWNTO 0);
	SIGNAL C23 : std_logic_vector(23 DOWNTO 0);
	SIGNAL S34 : std_logic_vector(23 DOWNTO 1);
	SIGNAL S3_4: std_logic_vector(23 DOWNTO 0);
	SIGNAL C34 : std_logic_vector(23 DOWNTO 0);
	SIGNAL S45 : std_logic_vector(23 DOWNTO 1);
BEGIN
	b1:OneSlice PORT MAP (InA,InB(0), SumIn, CarryIn, S12, C12);
	S1_2(23) <= '0';
	S1_2(22 DOWNTO 0) <= S12(23 DOWNTO 1);
	b2:OneSlice PORT MAP (InA,InB(1), S1_2, C12, S23, C23);
	S2_3(23) <= '0';
	S2_3(22 DOWNTO 0) <= S23(23 DOWNTO 1);
	b3:OneSlice PORT MAP (InA,InB(2), S2_3, C23, S34, C34);
	S3_4(23) <= '0';
	S3_4(22 DOWNTO 0) <= S34(23 DOWNTO 1);
	b4:OneSlice PORT MAP (InA,InB(3), S3_4, C34, S45, CarryOut);
	SumOut(22 DOWNTO 0) <= S45(23 DOWNTO 1);
END behv;
--------------------------------------------------------------
-- Copyright 1999 by NC State University All rights reserved.
--
-- Design:	GENERIC Pipeline slice OF the multpilier
-- Name:		Ibrahim Sahin
--	
-- Date:		March 2000
-- Description:
-- Pipelined.
--------------------------------------------------------------
Library IEEE;  
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--use WORK.all;
ENTITY LastSlice IS
	PORT(InA		: IN std_logic_vector(23 DOWNTO 0);
		InB		: IN std_logic;
		SumIn	: IN std_logic_vector(23 DOWNTO 0);
		CarryIn	: IN std_logic_vector(23 DOWNTO 0);
		SumOut	: OUT std_logic_vector(23 DOWNTO 0);
		CarryOut	: OUT std_logic_vector(23 DOWNTO 0));
END LastSlice;
ARCHITECTURE behv OF LastSlice IS
	SIGNAL AB : std_logic_vector(23 DOWNTO 0);
BEGIN
	loop1:FOR i IN 23 DOWNTO 0 GENERATE
			AB(i) <= InA(i) and InB;
		END GENERATE;
	loop2:FOR i IN 23 DOWNTO 0 GENERATE
		SumOut(i)	<= AB(i) xor SumIn(i) xor CarryIn(i);
		CarryOut(i) <= (AB(i) and SumIn(i)) or (AB(i) and CarryIn(i)) or (SumIn(i) and CarryIn(i));
	END GENERATE;
END behv;
--------------------------------------------------------------
-- Copyright 1999 by NC State University All rights reserved.
--
-- Design:	GENERIC Pipeline Block OF the multiplier
-- Name:		Ibrahim Sahin
--	
-- Date:		March 2000
-- Description:
-- Pipelined.
--------------------------------------------------------------
Library IEEE;  
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--use WORK.all;
ENTITY LastBlock IS
	PORT(InA		: IN std_logic_vector(23 DOWNTO 0);
		InB		: IN std_logic_vector(3 DOWNTO 0);
		SumIn	: IN std_logic_vector(23 DOWNTO 0);
		CarryIn	: IN std_logic_vector(23 DOWNTO 0);
		SumOut	: OUT std_logic_vector(22 DOWNTO 0);
		CarryOut	: OUT std_logic_vector(23 DOWNTO 0);
		ResOut	: OUT std_logic_vector(3 DOWNTO 0));
END LastBlock;
ARCHITECTURE behv OF LastBlock IS
	COMPONENT LastSlice
		PORT(InA		: IN std_logic_vector(23 DOWNTO 0);
			InB		: IN std_logic;
			SumIn	: IN std_logic_vector(23 DOWNTO 0);
			CarryIn	: IN std_logic_vector(23 DOWNTO 0);
			SumOut	: OUT std_logic_vector(23 DOWNTO 0);
			CarryOut	: OUT std_logic_vector(23 DOWNTO 0));
	END COMPONENT;
	SIGNAL S12 : std_logic_vector(23 DOWNTO 0);
	SIGNAL S1_2: std_logic_vector(23 DOWNTO 0);
	SIGNAL C12 : std_logic_vector(23 DOWNTO 0);
	SIGNAL S23 : std_logic_vector(23 DOWNTO 0);
	SIGNAL S2_3: std_logic_vector(23 DOWNTO 0);
	SIGNAL C23 : std_logic_vector(23 DOWNTO 0);
	SIGNAL S34 : std_logic_vector(23 DOWNTO 0);
	SIGNAL S3_4: std_logic_vector(23 DOWNTO 0);
	SIGNAL C34 : std_logic_vector(23 DOWNTO 0);
	SIGNAL S45 : std_logic_vector(23 DOWNTO 0);
BEGIN
	b1:LastSlice PORT MAP (InA,InB(0), SumIn, CarryIn, S12, C12);
	S1_2(23) <= '0';
	S1_2(22 DOWNTO 0) <= S12(23 DOWNTO 1);
	ResOut(0) <= S12(0);
	b2:LastSlice PORT MAP (InA,InB(1), S1_2, C12, S23, C23);
	S2_3(23) <= '0';
	S2_3(22 DOWNTO 0) <= S23(23 DOWNTO 1);
	ResOut(1) <= S23(0);
	b3:LastSlice PORT MAP (InA,InB(2), S2_3, C23, S34, C34);
	S3_4(23) <= '0';
	S3_4(22 DOWNTO 0) <= S34(23 DOWNTO 1);
	ResOut(2) <= S34(0);
	b4:LastSlice PORT MAP (InA,InB(3), S3_4, C34, S45, CarryOut);
	SumOut(22 DOWNTO 0) <= S45(23 DOWNTO 1);
	ResOut(3) <= S45(0);
END behv;
--------------------------------------------------------------
-- Copyright 1999 by NC State University All rights reserved.
--
-- Design:	GENERIC pipelined multiplier core
-- Name:		Ibrahim Sahin
--	
-- Date:		March 2000
-- Description:
-- Pipelined.
--------------------------------------------------------------
Library IEEE;  
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
--use WORK.all;
ENTITY int_core IS
	PORT(Clk   : IN  std_logic;
		Reset : IN  std_logic;
		Run   : IN  std_logic;
		InA   : IN  std_logic_vector(23 DOWNTO 0);
		InB   : IN  std_logic_vector(23 DOWNTO 0);
		Result: OUT std_logic_vector(47 DOWNTO 20));
END int_core;
ARCHITECTURE core_a OF int_core IS
	COMPONENT OneBlock
		PORT(InA		: IN std_logic_vector(23 DOWNTO 0);
			InB		: IN std_logic_vector(3 DOWNTO 0);
			SumIn	: IN std_logic_vector(23 DOWNTO 0);
			CarryIn	: IN std_logic_vector(23 DOWNTO 0);
			SumOut	: OUT std_logic_vector(22 DOWNTO 0);
			CarryOut	: OUT std_logic_vector(23 DOWNTO 0));
	END COMPONENT;
	COMPONENT LastBlock
		PORT(InA		: IN std_logic_vector(23 DOWNTO 0);
			InB		: IN std_logic_vector(3 DOWNTO 0);
			SumIn	: IN std_logic_vector(23 DOWNTO 0);
			CarryIn	: IN std_logic_vector(23 DOWNTO 0);
			SumOut	: OUT std_logic_vector(22 DOWNTO 0);
			CarryOut	: OUT std_logic_vector(23 DOWNTO 0);
			ResOut	: OUT std_logic_vector(3 DOWNTO 0));
	END COMPONENT;
	COMPONENT reg_g
		GENERIC(width : integer:= 4);
		PORT(Clk		: IN std_logic;
			Reset	: IN std_logic;
			Run		: IN std_logic;
			Datain	: IN std_logic_vector(width-1 DOWNTO 0);
			Q		: OUT std_logic_vector(width-1 DOWNTO 0));
	END COMPONENT;
	COMPONENT full_adder
		PORT(a	: IN std_logic;
			b	: IN std_logic;
			cin	: IN std_logic;
			s	: OUT std_logic;
			cout	: OUT std_logic);
	END COMPONENT;
	SIGNAL zero_v		: std_logic_vector(23 DOWNTO 0);
	SIGNAL zero		: std_logic;
	SIGNAL InA23		: std_logic_vector(23 DOWNTO 0);
	SIGNAL InA34		: std_logic_vector(23 DOWNTO 0);
	SIGNAL InA45		: std_logic_vector(23 DOWNTO 0);
	SIGNAL InA56		: std_logic_vector(23 DOWNTO 0);
	SIGNAL InA67		: std_logic_vector(23 DOWNTO 0);
	SIGNAL InB23		: std_logic_vector(23 DOWNTO 4);
	SIGNAL InB34		: std_logic_vector(23 DOWNTO 8);
	SIGNAL InB45		: std_logic_vector(23 DOWNTO 12);
	SIGNAL InB56		: std_logic_vector(23 DOWNTO 16);
	SIGNAL InB67		: std_logic_vector(23 DOWNTO 20);
	SIGNAL ResOut12	: std_logic_vector(3 DOWNTO 0);
	SIGNAL ResOut23	: std_logic_vector(7 DOWNTO 0);
	SIGNAL ResOut34	: std_logic_vector(11 DOWNTO 0);
	SIGNAL ResOut45	: std_logic_vector(15 DOWNTO 0);
	SIGNAL ResOut56	: std_logic_vector(19 DOWNTO 0);
	SIGNAL ResOut67	: std_logic_vector(23 DOWNTO 20);
	SIGNAL CarryOut12	: std_logic_vector(23 DOWNTO 0);
	SIGNAL CarryOut23	: std_logic_vector(23 DOWNTO 0);
	SIGNAL CarryOut34	: std_logic_vector(23 DOWNTO 0);
	SIGNAL CarryOut45	: std_logic_vector(23 DOWNTO 0);
	SIGNAL CarryOut56	: std_logic_vector(23 DOWNTO 0);
	SIGNAL CarryOut67	: std_logic_vector(23 DOWNTO 0);
	SIGNAL CarryIn12	: std_logic_vector(23 DOWNTO 0);
	SIGNAL CarryIn23	: std_logic_vector(23 DOWNTO 0);
	SIGNAL CarryIn34	: std_logic_vector(23 DOWNTO 0);
	SIGNAL CarryIn45	: std_logic_vector(23 DOWNTO 0);
	SIGNAL CarryIn56	: std_logic_vector(23 DOWNTO 0);
	--SIGNAL CarryIn67	: std_logic_vector(23 DOWNTO 0);
	SIGNAL SumOut12	: std_logic_vector(22 DOWNTO 0); 
	SIGNAL SumOut23	: std_logic_vector(22 DOWNTO 0); 
	SIGNAL SumOut34	: std_logic_vector(22 DOWNTO 0); 
	SIGNAL SumOut45	: std_logic_vector(22 DOWNTO 0); 
	SIGNAL SumOut56	: std_logic_vector(22 DOWNTO 0); 
	SIGNAL SumOut67	: std_logic_vector(22 DOWNTO 0); 
	SIGNAL SumIn12		: std_logic_vector(23 DOWNTO 0); 
	SIGNAL SumIn23		: std_logic_vector(23 DOWNTO 0); 
	SIGNAL SumIn34		: std_logic_vector(23 DOWNTO 0); 
	SIGNAL SumIn45		: std_logic_vector(23 DOWNTO 0); 
	SIGNAL SumIn56		: std_logic_vector(23 DOWNTO 0); 
	--SIGNAL SumIn67		: std_logic_vector(23 DOWNTO 0); 
	SIGNAL Carry		: std_logic_vector(23 DOWNTO 0);
	SIGNAL ResOut99	: std_logic_vector(47 DOWNTO 24);
BEGIN
	zero_v	<= "000000000000000000000000";
	zero		<= '0';
	RA1:reg_g GENERIC MAP (24)					-- registers for A
			PORT MAP (Clk, Reset, Run, InA, InA23);
	RA2:reg_g GENERIC MAP (24)
			PORT MAP (Clk, Reset, Run, InA23, InA34);
	RA3:reg_g GENERIC MAP (24)
			PORT MAP (Clk, Reset, Run, InA34, InA45);
	RA4:reg_g GENERIC MAP (24)
			PORT MAP (Clk, Reset, Run, InA45, InA56);
	RA5:reg_g GENERIC MAP (24)
			PORT MAP (Clk, Reset, Run, InA56, InA67);
	RB1:reg_g GENERIC MAP (20)					-- registers for B
			PORT MAP (Clk, Reset, Run, InB(23 DOWNTO 4), InB23);
	RB2:reg_g GENERIC MAP (16)
			PORT MAP (Clk, Reset, Run, InB23(23 DOWNTO 8), InB34);
	RB3:reg_g GENERIC MAP (12)
			PORT MAP (Clk, Reset, Run, InB34(23 DOWNTO 12), InB45);
	RB4:reg_g GENERIC MAP (8)
			PORT MAP (Clk, Reset, Run, InB45(23 DOWNTO 16), InB56);
	RB5:reg_g GENERIC MAP (4)
			PORT MAP (Clk, Reset, Run, InB56(23 DOWNTO 20), InB67);
	RS1:reg_g GENERIC MAP (23)					-- registers for sum
			PORT MAP (Clk, Reset, Run, SumOut12, SumIn12(22 DOWNTO 0));
			SumIn12(23) <= zero;
	RS2:reg_g GENERIC MAP (23)
			PORT MAP (Clk, Reset, Run, SumOut23, SumIn23(22 DOWNTO 0));
			SumIn23(23) <= zero;
	RS3:reg_g GENERIC MAP (23)
			PORT MAP (Clk, Reset, Run, SumOut34, SumIn34(22 DOWNTO 0));
			SumIn34(23) <= zero;
	RS4:reg_g GENERIC MAP (23)
			PORT MAP (Clk, Reset, Run, SumOut45, SumIn45(22 DOWNTO 0));
			SumIn45(23) <= zero;
	RS5:reg_g GENERIC MAP (23)
			PORT MAP (Clk, Reset, Run, SumOut56, SumIn56(22 DOWNTO 0));
			SumIn56(23) <= zero;
--	RS6:reg_g GENERIC MAP (23)							-----------------------------
	--		PORT MAP (Clk, Reset, Run, SumOut67, SumIn67(22 DOWNTO 0));
		--	SumIn67(23) <= zero;
	RC1:reg_g GENERIC MAP (24)					-- registers for carry
			PORT MAP (Clk, Reset, Run, CarryOut12, CarryIn12);
	RC2:reg_g GENERIC MAP (24)
			PORT MAP (Clk, Reset, Run, CarryOut23, CarryIn23);
	RC3:reg_g GENERIC MAP (24)
			PORT MAP (Clk, Reset, Run, CarryOut34, CarryIn34);
	RC4:reg_g GENERIC MAP (24)
			PORT MAP (Clk, Reset, Run, CarryOut45, CarryIn45);
	RC5:reg_g GENERIC MAP (24)
			PORT MAP (Clk, Reset, Run, CarryOut56, CarryIn56);
--	RC6:reg_g GENERIC MAP (24)							-----------------------------
	--		PORT MAP (Clk, Reset, Run, CarryOut67, CarryIn67);
--	RR1:reg_g GENERIC MAP (4)					-- registers for result
--			PORT MAP (Clk, Reset, Run, ResOut12, ResOut23(3 DOWNTO 0));
--	RR2:reg_g GENERIC MAP (8)
--			PORT MAP (Clk, Reset, Run, ResOut23, ResOut34(7 DOWNTO 0));
--	RR3:reg_g GENERIC MAP (12)
--			PORT MAP (Clk, Reset, Run, ResOut34, ResOut45(11 DOWNTO 0));
--	RR4:reg_g GENERIC MAP (16)
--			PORT MAP (Clk, Reset, Run, ResOut45, ResOut56(15 DOWNTO 0));
--	RR5:reg_g GENERIC MAP (20)
--			PORT MAP (Clk, Reset, Run, ResOut56, ResOut67(19 DOWNTO 0));
	RR6:reg_g GENERIC MAP (4)
			PORT MAP (Clk, Reset, Run, ResOut67, Result(23 DOWNTO 20));
	RR9:reg_g GENERIC MAP(24)					-- register for most significant half of the result
			PORT MAP (Clk, Reset, Run, ResOut99, Result(47 DOWNTO 24));
	b1: OneBlock PORT MAP (InA, InB(3 DOWNTO 0), zero_v, zero_v, SumOut12, CarryOut12);
	b2: OneBlock PORT MAP (InA23, InB23(7 DOWNTO 4), SumIn12, CarryIn12, SumOut23, CarryOut23);
	b3: OneBlock PORT MAP (InA34, InB34(11 DOWNTO 8), SumIn23, CarryIn23, SumOut34, CarryOut34);
	b4: OneBlock PORT MAP (InA45, InB45(15 DOWNTO 12), SumIn34, CarryIn34, SumOut45, CarryOut45);
	b5: OneBlock PORT MAP (InA56, InB56(19 DOWNTO 16), SumIn45, CarryIn45, SumOut56, CarryOut56);
	b6: LastBlock PORT MAP (InA67, InB67(23 DOWNTO 20), SumIn56, CarryIn56, SumOut67, CarryOut67, ResOut67(23 DOWNTO 20));
	PROCESS (SumOut67,CarryOut67)	
		VARIABLE AA			: std_logic_vector(23 DOWNTO 0);
		VARIABLE BB			: std_logic_vector(23 DOWNTO 0);
		VARIABLE AddOut		: std_logic_vector(23 DOWNTO 0);
	BEGIN
		AA(23) := Zero;
		AA(22 DOWNTO 0) := SumOut67(22 DOWNTO 0);
		BB(23 DOWNTO 0) := CarryOut67(23 DOWNTO 0);
		AddOut := AA + BB;
		ResOut99(47 DOWNTO 24) <= AddOut(23 DOWNTO 0);
	END PROCESS;
--	fa1: full_adder PORT MAP (SumOut67(0), CarryOut67(0), Zero, ResOut99(24), Carry(0));
--	lp1:	FOR i IN 1 TO 22 GENERATE
--			f_a: full_adder PORT MAP(SumOut67(i), CarryOut67(i), Carry(i-1), ResOut99(24+i), Carry(i)); 
--		END GENERATE;
--	fa24:full_adder PORT MAP (Zero, CarryOut67(23), Carry(22), ResOut99(47), Carry(23));
END core_a;
--------------------------------------------------------------
-- Copyright 1999 by NC State University All rights reserved.
--
-- Design: Floating Point Multiplier
-- Name:    Clay Gloster
--	
-- Date:    October 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."*";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY AddExp IS
	PORT(clk	: in std_logic;
		reset: in std_logic;
		EnR	: in std_logic;
		EnL	: in std_logic;
		Exp_A: in std_logic_vector(7 downto 0);
		Exp_B: in std_logic_vector(7 downto 0);
		SignA: in std_logic;
		SignB: in std_logic;
		Exp	: out std_logic_vector(7 downto 0); 
		Sign : out std_logic;
		RunO	: out std_logic);
END AddExp;
ARCHITECTURE RTL OF AddExp IS
BEGIN
	PROCESS (CLK,reset)
		variable ExpAPrime : std_logic_vector(7 downto 0);
	BEGIN
		IF (clk = '1' and clk'event) THEN
			IF (reset = '1') THEN
				Exp <= (Others=> '0');
				Sign <= '0';
				RunO <= '0';
			ELSE 
				RunO <= EnR and EnL;
				IF (EnR = '1' and EnL = '1') THEN
					ExpAPrime := Exp_A + "10000001"; -- Subtract 127 from ExpA
					Exp <= Exp_B + ExpAPrime;
					Sign <= SignA XOR SignB;
				END IF; -- END IF Run= '1'
			END IF; -- END IF reset = 0
		END IF; -- END IF clk = '1' and clk'event
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 2000 by NC State University All rights reserved.
--
-- Design: 9 bit register
-- Name:    Ibrahim Sahin
--	
-- Date:    April 2000
-- Description:
--  Pipelined.
--------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_Logic_1164.all;
ENTITY reg10 IS
	PORT(Datain	: IN std_logic_vector(8 DOWNTO 0);
		Ck		: IN std_logic;
		Reset	: IN std_logic;
		Run		: IN std_logic;
		Q		: OUT std_logic_vector(8 DOWNTO 0);
		RunO		: OUT std_logic);
END reg10;
ARCHITECTURE RTL OF reg10 IS
	SIGNAL D : std_logic_vector(8 DOWNTO 0);
BEGIN
	PROCESS
	BEGIN
		WAIT UNTIL ((Ck'EVENT) AND (Ck= '1'));
		IF (Reset = '1') THEN 		 -- Changed Reset to Active High
			D <= "000000000";
			RunO <= '0';
		ELSE
			RunO <= Run;
			IF (Run = '1') THEN
				D <= Datain;
			ELSE
				D <= D;
			END IF;
		END IF ;
	END process;
	Q <= D;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by NC State University All rights reserved.
--
-- Design: Floating Point Adder
-- Name:    Clay Gloster
--	
-- Date:    June 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY MultNorm1 IS
	PORT(clk		:  IN std_logic;
		reset	:  IN std_logic;
		Run		:  IN std_logic;
 		UMan		:  IN std_logic_vector (47 DOWNTO 20);
		UExp		:  IN std_logic_vector ( 8 DOWNTO 0);
		zeroflag	: IN std_logic_vector(1 downto 0);
		Result	: OUT std_logic_vector (31 DOWNTO 0);
		RunO		: OUT std_logic);
END MultNorm1;
ARCHITECTURE RTL OF MultNorm1 IS
BEGIN
	PROCESS (CLK,reset)
		variable ExpPrime : std_logic_vector(7 downto 0);
	BEGIN
		IF (clk = '1' and clk'event) THEN
			IF (reset = '1') THEN
				Result <= (OTHERS  => '0');
			ELSE
				RunO <= Run;
				IF (Run = '1') AND (ZEROFLAG = "00") THEN
					Result(31) <= UExp(8); 
					--exp := UExp(7 downto 0);
					IF (UMan(47) = '0') THEN -- No need to adjust exponents
						Result(30 DOWNTO 23) <= UExp(7 DOWNTO 0);
						Result(22 DOWNTO 0) <= Uman(45 DOWNTO 23);
					ELSE 	-- We need to adjust down
						ExpPrime := UExp(7 DOWNTO 0);
						Result(30 DOWNTO 23) <= ExpPrime + "00000001";
						Result(22 DOWNTO 0) <= Uman(46 DOWNTO 24);
					END IF; --END IF Uman(47) = '0'
				ELSIF (RUN = '1') AND (ZEROFLAG = "10") then
				  Result <= (OTHERS  => '0');
				ELSIF (RUN = '1') AND (ZEROFLAG = "01") then
				  Result <= "11111111111111111111111111111111";
				END IF; -- END Run = '1'
			END IF; -- END IF reset = 0
		END IF; -- END IF clk = '1' and clk'event
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by NC State University All rights reserved.
--
-- Design: Floating Point Adder
-- Name:    Clay Gloster
--	
-- Date:    June 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
--------------------------------------------------------------
-- Copyright 1999 by NC State University All rights reserved.
--
-- Design: Six Stage Floating Point Adder Core
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    November 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_Logic_1164.all;
ENTITY MultRegStage8 IS
	PORT(Ck		: IN std_logic;
		Reset	: IN std_logic;
		Run		: IN std_logic;
		Datain	: IN std_logic_vector(31 DOWNTO 0);
		Q		: OUT std_logic_vector(31 DOWNTO 0);
		RunO		: OUT std_logic);
END MultRegStage8;
ARCHITECTURE RTL OF MultRegStage8 IS
	SIGNAL D : std_logic_vector(31 DOWNTO 0);
	SIGNAL R : std_logic;
BEGIN
	PROCESS
	BEGIN
		WAIT UNTIL ((Ck'EVENT) AND (Ck= '1'));
		IF (Reset = '1') THEN 		 -- Changed Reset to Active High
			D <= "00000000000000000000000000000000";
			R <= '0';
		ELSIF (Run = '1') THEN
			D <= Datain;
			R <= Run;
		ELSE
			D <= D;
			R <= Run;
		END IF;
	END process;
	Q <= D;
	RunO <= R;
END RTL;
---------------------------------------------------------------
library IEEE;
use IEEE.STD_Logic_1164.all;
entity MULT_REG_GENERIC is
generic (Width : integer);
port (Datain : in std_logic_vector(Width-1 downto 0);
Clk,Reset : in std_logic;
Q: out std_logic_vector(Width-1 downto 0) );
end MULT_REG_GENERIC;
architecture RTL of MULT_REG_GENERIC is
begin
start: process(Clk)
variable i: integer;
begin
if (Clk'EVENT and Clk = '1') then
 if (Reset = '1') then  -- Changed Reset to Active High
  for i in 0 to Width-1 loop
   Q(i) <= '0';
  end loop;
 else
 Q <= Datain;
 end if;
end if;
end process;
end RTL;
---------------------------------------------------------------
library IEEE;
use IEEE.STD_Logic_1164.all;
entity mult_register2d is
generic (Height, Width : integer);
port (Datain : in std_logic_vector(Width-1 downto 0);
Clk,Reset : in std_logic;
Q: out std_logic_vector(Width-1 downto 0) );
end mult_register2d;
architecture structural of mult_register2d is
component MULT_REG_GENERIC 
  generic (Width : integer);
  port (Datain : in std_logic_vector(Width-1 downto 0);
        Clk,Reset : in std_logic;
        Q: out std_logic_vector(Width-1 downto 0) );
end component;
type anarray is array ( 0 to Height) of std_logic_vector(Width-1 downto 0);
signal REGIO : anarray;
begin
 lpp1: for i in  0 to Height-1 generate
 I0:   MULT_REG_GENERIC generic map (Width)
       port map ( REGIO(i), Clk, Reset, REGIO(i+1) ); 
        end generate;
 REGIO(0) <= Datain;
 Q <= REGIO(Height);
end structural;
---------------------------------------------------------------
--------------------------------------------------------------
library IEEE;
use IEEE.STD_Logic_1164.all;
use IEEE.std_logic_unsigned."+";
entity StageMBZ is
port (A,B : in std_logic_vector(31 downto 0);
Clk,Reset : in std_logic;
Q: out std_logic_vector(1 downto 0) );
end StageMBZ;
architecture RTL of StageMBZ is
begin
start: process(Clk)
variable tempexponent,tempA,tempB: std_logic_vector(7 downto 0);
begin
if (Clk'EVENT and Clk = '1') then
 if (Reset = '1') then  -- Changed Reset to Active High
        Q <= "00";
 else
	tempA := A(30 downto 23);
	tempB := B(30 downto 23);
	tempA := tempA + "10000001";
	tempB := tempB + "10000001";
	tempexponent := tempA + tempB;
        if ( A = "00000000000000000000000000000000") OR 
	   (B="00000000000000000000000000000000") then
        	Q <= "10";
        elsif ( ( tempA(7) AND tempB(7) and NOT (tempexponent(7)) ) = '1' ) then
		Q <= "10";
	elsif ( ( NOT(tempA(7)) AND NOT(tempB(7)) and tempexponent(7) ) = '1' ) then
		Q <= "01";
	else 
        	Q <= "00";
        end if;
 end if;
end if;
end process;
end RTL;
library IEEE;
use IEEE.STD_Logic_1164.all;
entity multbyzero is
port (A,B : in std_logic_vector(31 downto 0);
Clk,Reset : in std_logic;
Q: out std_logic_vector(1 downto 0) );
end multbyzero;
architecture structural of multbyzero is
component mult_register2d
generic (Height, Width : integer);
port (Datain : in std_logic_vector(Width-1 downto 0);
Clk,Reset : in std_logic;
Q: out std_logic_vector(Width-1 downto 0) );
end component;
component StageMBZ
port (A,B : in std_logic_vector(31 downto 0);
Clk,Reset : in std_logic;
Q: out std_logic_vector(1 downto 0) );
end component;
signal Serror : std_logic_vector(1 downto 0);
signal VSerror,VSQ : std_logic_vector(1 downto 0);
begin
 I0:   StageMBZ  port map (A,B,Clk,Reset,Serror);
 I1:   mult_register2d generic map(5,2) -- Total of Six Stages before Normalize unit
       port map (Serror,Clk,Reset,Q);
end structural;
--------------------------------------------------------------
-- Copyright 2000 by NC State University All rights reserved.
--
-- Design:	Floating Point Multiplier Core
-- Name:		Ibrahim Sahin
--	
-- Date:    April 2000
-- Description:
-- Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
ENTITY FpMultCore_8 IS
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		EnR		: IN std_logic;
		EnL		: IN std_logic;
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		Op_Q		: OUT std_logic_vector(31 DOWNTO 0);
		EnN		: OUT std_logic);
END FpMultCore_8;
ARCHITECTURE STRUCTURAL OF FpMultCore_8 IS
COMPONENT AddExp
	PORT(clk	: in std_logic;
		reset: in std_logic;
		EnR	: in std_logic;
		EnL	: in std_logic;
		Exp_A: in std_logic_vector(7 downto 0);
		Exp_B: in std_logic_vector(7 downto 0);
		SignA: in std_logic;
		SignB: in std_logic;
		Exp	: out std_logic_vector(7 downto 0); 
		Sign : out std_logic;
		RunO	: out std_logic);
END COMPONENT;
COMPONENT reg10
	PORT(Datain	: IN std_logic_vector(8 DOWNTO 0);
		Ck		: IN std_logic;
		Reset	: IN std_logic;
		Run		: IN std_logic;
		Q		: OUT std_logic_vector(8 DOWNTO 0);
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT int_core
	PORT(Clk   : IN  std_logic;
		Reset : IN  std_logic;
		Run   : IN  std_logic;
		InA   : IN  std_logic_vector(23 DOWNTO 0);
		InB   : IN  std_logic_vector(23 DOWNTO 0);
		Result: OUT std_logic_vector(47 DOWNTO 20));
END COMPONENT;
COMPONENT multiply_new
	GENERIC(width : integer; 	  
		   digit : integer;    -- digit = width/stage
		   stage : integer);
	PORT(clk   : IN  std_logic;
		reset : IN  std_logic;
		InA   : IN  std_logic_vector(width-1 DOWNTO 0);
		InB   : IN  std_logic_vector(width-1 DOWNTO 0);
		dummy : IN  std_logic;
		load  : IN  std_logic;
		Result: OUT std_logic_vector((width*2)-1 DOWNTO 0));
END COMPONENT;
COMPONENT MultNorm1
	PORT(clk		:  IN std_logic;
		reset	:  IN std_logic;
		Run		:  IN std_logic;
 		UMan		:  IN std_logic_vector (47 DOWNTO 20);
		UExp		:  IN std_logic_vector ( 8 DOWNTO 0);
		zeroflag 	: in std_logic_vector(1 downto 0);
		Result	: OUT std_logic_vector (31 DOWNTO 0);
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT MultRegStage8
	PORT(Ck		: IN std_logic;
		Reset	: IN std_logic;
		Run		: IN std_logic;
		Datain	: IN std_logic_vector(31 DOWNTO 0);
		Q		: OUT std_logic_vector(31 DOWNTO 0);
		RunO		: OUT std_logic);
END COMPONENT;
component multbyzero 
port (A,B : in std_logic_vector(31 downto 0);
Clk,Reset : in std_logic;
Q: out std_logic_vector(1 downto 0) );
end component;
SIGNAL Op_A01	: std_logic_vector (23 DOWNTO 0);
SIGNAL Op_B01	: std_logic_vector (23 DOWNTO 0);
SIGNAL Zero	: std_logic;  
SIGNAL One	: std_logic;
SIGNAL Exp12	: std_logic_vector (8 DOWNTO 0);
SIGNAL Exp23	: std_logic_vector (8 DOWNTO 0);
SIGNAL Exp34	: std_logic_vector (8 DOWNTO 0);
SIGNAL Exp45	: std_logic_vector (8 DOWNTO 0);
SIGNAL Exp56	: std_logic_vector (8 DOWNTO 0);
SIGNAL Exp67	: std_logic_vector (8 DOWNTO 0);
SIGNAL RunO12	: std_logic;
SIGNAL RunO23	: std_logic;
SIGNAL RunO34	: std_logic;
SIGNAL RunO45	: std_logic;
SIGNAL RunO56	: std_logic;
SIGNAL RunO67	: std_logic;
SIGNAL Result67: std_logic_vector (47 DOWNTO 20);
SIGNAL ExpCor78: std_logic_vector (7 DOWNTO 0);
SIGNAL ShfDst78: std_logic_vector (4 DOWNTO 0);
SIGNAL OMan78	: std_logic_vector (47 DOWNTO 0);
SIGNAL OExp78	: std_logic_vector (8 DOWNTO 0);
SIGNAL RunO78	: std_logic;
SIGNAL Result78: std_logic_vector (31 DOWNTO 0);
SIGNAL MultByZeroFlag: std_logic_vector(1 downto 0);
BEGIN
	Inst_Exp: AddExp PORT MAP(clk,reset,EnR,EnL,Op_A(30 DOWNTO 23),Op_B(30 DOWNTO 23),
	Op_A(31),Op_B(31),Exp12(7 DOWNTO 0),Exp12(8),RunO12);
	Ints_R1 : reg10 PORT MAP (Exp12, clk, reset, RunO12, Exp23, RunO23);
	Ints_R2 : reg10 PORT MAP (Exp23, clk, reset, RunO23, Exp34, RunO34);
	Ints_R3 : reg10 PORT MAP (Exp34, clk, reset, RunO34, Exp45, RunO45);
	Ints_R4 : reg10 PORT MAP (Exp45, clk, reset, RunO45, Exp56, RunO56);
	Ints_R5 : reg10 PORT MAP (Exp56, clk, reset, RunO56, Exp67, RunO67);
	Op_A01(22 DOWNTO 0) <=Op_A(22 DOWNTO 0);
	Op_A01(23) <= '1';
	Op_B01(22 DOWNTO 0) <=Op_B(22 DOWNTO 0);
	Op_B01(23) <= '1';
	Zero		<= '0';
	One		<= '1';
	Inst_Mul: int_core PORT MAP (clk, reset, One, Op_A01, Op_B01, Result67);
	Inst_N1 : MultNorm1 PORT MAP (clk, reset, RunO67, Result67, Exp67(8 DOWNTO 0), MultByZeroFlag, Result78, RunO78);
	Inst_R8 : MultRegStage8 PORT MAP (clk, reset, RunO78, Result78, Op_Q, EnN);
	Inst_MBZ: multbyzero PORT MAP (Op_A,Op_B,Clk,Reset,MultByZeroFlag);
END STRUCTURAL;