--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design Name : 8 stage pipelined Floating Point Adder and 8 stage 
--			Floating point Subtractor Core (See bottom of file)
-- Name		: Ibrahim Sahin & Clay Gloster
-- Date 		: September 2001
-- Description	:
--------------------------------------------------------------
-----------------PARTS IN THE ADDER---------------------------
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: SubCompareExp
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    October 1999
-- Description: This is the first stage of the subtractor, it complements the 
-- Sign Bit.
-- Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_arith.all;
ENTITY SubCompareExp IS
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		EnR		: IN std_logic;
		EnL		: IN std_logic;
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		LExp		: OUT std_logic_vector(7 DOWNTO 0);
		SExp		: OUT std_logic_vector(7 DOWNTO 0);
		LMan		: OUT std_logic_vector(22 DOWNTO 0); 
		SMan		: OUT std_logic_vector(22 DOWNTO 0);	   
		LSign	: OUT std_logic;
		SSign	: OUT std_logic;
		RunO		: OUT std_logic);
END SubCompareExp;
ARCHITECTURE RTL OF SubCompareExp IS
BEGIN
	PROCESS (CLK,reset)
		variable expA,expB: std_logic_vector(8 DOWNTO 0);
	BEGIN
		IF (clk = '1' and clk'event) THEN
			IF (reset = '1') THEN
				LExp <= (Others=> '0');
				SExp <= (Others=> '0');
				LMan <= (Others=> '0');
				SMan <= (Others=> '0');
				LSign <= '0';
				SSign <= '0';
				RunO <= '0';
			ELSE
				RunO <= EnR and EnL;
				IF (EnR = '1' and EnL = '1') THEN
					expA := '0' & Op_A(30 DOWNTO 23);
					expB := '0' & Op_B(30 DOWNTO 23);
					IF (expA > expB) THEN
						IF (Op_B(30 DOWNTO 0) = "0000000000000000000000000000000") THEN
							SSign <= '0';
						ELSE
							SSign <= not Op_B(31);
						END IF;
						SExp <=  Op_B(30 DOWNTO 23);
						SMan <= Op_B(22 DOWNTO 0);
						LSign <= Op_A(31);
						LExp <= Op_A(30 DOWNTO 23);
						LMan <= Op_A(22 DOWNTO 0);
					ELSE
						SSign <= Op_A(31);
						SExp <=  Op_A(30 DOWNTO 23);
						SMan <= Op_A(22 DOWNTO 0);
						IF (Op_B(30 DOWNTO 0) = "0000000000000000000000000000000") THEN
							LSign <= '0';
						ELSE				
							LSign <= not Op_B(31);
						END IF;
						LExp <= Op_B(30 DOWNTO 23);
						LMan <= Op_B(22 DOWNTO 0);
					END IF;
				END IF; -- END IF EnCompareExp = '1'
			END IF; -- END IF reset = 0
		END IF; -- END IF clk = '1' and clk'event
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: CompareExp
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    October 1999
-- Description: This is the first stage of the adder core
-- Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_arith.all;
ENTITY CompareExp IS
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		EnR		: IN std_logic;
		EnL		: IN std_logic;
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		LExp		: OUT std_logic_vector(7 DOWNTO 0);
		SExp		: OUT std_logic_vector(7 DOWNTO 0);
		LMan		: OUT std_logic_vector(22 DOWNTO 0); 
		SMan		: OUT std_logic_vector(22 DOWNTO 0);	   
		LSign	: OUT std_logic;
		SSign	: OUT std_logic;
		RunO		: OUT std_logic);
END CompareExp;
ARCHITECTURE RTL OF CompareExp IS
BEGIN
	PROCESS (CLK,reset)
		variable expA,expB: std_logic_vector(8 DOWNTO 0);
	BEGIN
		IF (clk = '1' and clk'event) THEN
			IF (reset = '1') THEN
				LExp <= (Others=> '0');
				SExp <= (Others=> '0');
				LMan <= (Others=> '0');
				SMan <= (Others=> '0');
				LSign <= '0';
				SSign <= '0';
				RunO <= '0';
			ELSE
				RunO <= EnR and EnL;
				IF (EnR = '1' and EnL = '1') THEN
					expA := '0' & Op_A(30 DOWNTO 23);
					expB := '0' & Op_B(30 DOWNTO 23);
					IF (expA > expB) THEN
						SSign <= Op_B(31);
						SExp <=  Op_B(30 DOWNTO 23);
						SMan <= Op_B(22 DOWNTO 0);
						LSign <= Op_A(31);
						LExp <= Op_A(30 DOWNTO 23);
						LMan <= Op_A(22 DOWNTO 0);
					ELSE
						SSign <= Op_A(31);
						SExp <=  Op_A(30 DOWNTO 23);
						SMan <= Op_A(22 DOWNTO 0);
						LSign <= Op_B(31);
						LExp <= Op_B(30 DOWNTO 23);
						LMan <= Op_B(22 DOWNTO 0);
					END IF;
				END IF; -- END IF EnCompareExp = '1'
			END IF; -- END IF reset = 0
		END IF; -- END IF clk = '1' and clk'event
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: ComputeShift
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    October 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHR;
use IEEE.std_logic_unsigned.CONV_INTEGER;
use IEEE.std_logic_misc.OR_REDUCE;
use IEEE.std_logic_arith.all;
ENTITY ComputeShift IS
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		SExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(22 DOWNTO 0);
		SMan		: IN std_logic_vector(22 DOWNTO 0);
		LSign	: IN std_logic;
		SSign	: IN std_logic;
		LExpP	: OUT std_logic_vector(7 DOWNTO 0);
		SExpP	: OUT std_logic_vector(7 DOWNTO 0);
		LManP	: OUT std_logic_vector(22 DOWNTO 0);
		SManP	: OUT std_logic_vector(22 DOWNTO 0);
		LSignP	: OUT std_logic;
		SSignP	: OUT std_logic;
		shiftdistance : OUT std_logic_vector(4 DOWNTO 0);
		RunO		: OUT std_logic);
END ComputeShift;
ARCHITECTURE RTL OF ComputeShift IS
BEGIN
	PROCESS (CLK,reset)
		variable sdistance: std_logic_vector(7 DOWNTO 0);
	BEGIN
		IF (clk = '1' and clk'event) THEN
			IF (reset = '1') THEN
				LExpP <= (Others=> '0');
				SExpP <= (Others=> '0');
				LManP <= (Others=> '0');
				SManP <= (Others=> '0');
				LSignP <= '0';
				SSignP <= '0';
				shiftdistance <= "00000";
			ELSE
				RunO <= Run;
				IF (Run = '1') THEN
					sdistance := LExp - SExp;
					LExpP <= LExp;
					SExpP<= SExp;
					LManP <= LMan;
					SManP<=SMan;
					LSignP <= LSign;
					SSignP <= SSign;
					shiftdistance <= sdistance(4 DOWNTO 0);
				END IF; -- END IF EnAlign = '1'
			END IF; -- END IF reset = 0
		END IF; -- END IF clk = '1' and clk'event
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: ShiftMan
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    October 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHR;
use IEEE.std_logic_unsigned.CONV_INTEGER;
use IEEE.std_logic_misc.OR_REDUCE;
use IEEE.std_logic_arith.all;
ENTITY ShiftMan IS
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		shiftdistance : IN std_logic_vector(4 DOWNTO 0); 
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		SExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(22 DOWNTO 0);
		SMan		: IN std_logic_vector(22 DOWNTO 0);
		LSign	: IN std_logic;
		SSign	: IN std_logic;
		LExpP	: OUT std_logic_vector(7 DOWNTO 0);
		LManP	: OUT std_logic_vector(24 DOWNTO 0);
		SManP	: OUT std_logic_vector(24 DOWNTO 0);
		LSignP	: OUT std_logic;
		SSignP	: OUT std_logic;
		RunO		: OUT std_logic);
END ShiftMan;
ARCHITECTURE RTL OF ShiftMan IS
BEGIN
	PROCESS (CLK,reset)
		variable manA,manB: std_logic_vector(24 DOWNTO 0);    
		variable bitA,bitB: std_logic;
	BEGIN
		IF (clk = '1' and clk'event) THEN
			IF (reset = '1') THEN
				LExpP <= (Others=> '0');
				LManP <= (Others=> '0');
				SManP <= (Others=> '0');
				LSignP <= '0';
				SSignP <= '0';
			ELSE
				RunO <= Run;
				IF (Run = '1') THEN
					-- Add Hidden Bits to Manitissas
					bitA := LSign OR OR_REDUCE(LMan) OR OR_REDUCE(LExp);
					manA := bitA&LMan(22 downto 0)&'0';
					bitB := SSign OR OR_REDUCE(SMan) OR OR_REDUCE(SExp);
					manB := bitB&SMan(22 downto 0)&'0';
					SManP <= SHR(manB,shiftdistance);
					LExpP <= LExp;
					LManP <= manA;
					LSignP <= LSign;
					SSignP <= SSign;
				END IF; -- END IF EnShiftMan = '1'
			END IF; -- END IF reset = 0
		END IF; -- END IF clk = '1' and clk'event
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: CompareMan
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    November 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
--use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY CompareMan IS
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		LSign	: IN std_logic;
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(24 DOWNTO 0);
		SSign	: IN std_logic;
		SMan		: IN std_logic_vector(24 DOWNTO 0);
		Exp		: OUT std_logic_vector(7 DOWNTO 0); 
		LMan1	: OUT std_logic_vector(24 DOWNTO 0);	    
		SMan1	: OUT std_logic_vector(24 DOWNTO 0);	    
		Sign		: OUT std_logic;
		AddSub 	: OUT std_logic;
		RunO		: OUT std_logic);
END CompareMan;
ARCHITECTURE RTL OF CompareMan IS
BEGIN
	PROCESS (CLK,reset)
	BEGIN
		IF (clk = '1' and clk'event) THEN
			IF (reset = '1') THEN
				Exp <= (Others=> '0');
				LMan1 <= (Others=> '0');
				SMan1 <= (Others=> '0');
				Sign <= '0';
				AddSub <= '0';
			ELSE
				RunO <= Run;
				IF (Run = '1') THEN
					IF (LSign = SSign) THEN -- Signs of the two numbers are the same
						Sign <= LSign;
						LMan1 <= LMan;
						SMan1 <= SMan;
						AddSub <= '0';
					ELSE -- Signs are different
						IF (LMan > SMan) THEN
							Sign <= LSign;
							AddSub <= '1';
							LMan1 <= LMan;
							SMan1 <= SMan;
						ELSE
							Sign <= SSign;
							AddSub <= '1';
							LMan1 <= SMan;
							SMan1 <= LMan;
						END IF;
					END IF; -- END IF LSIgn = SSign
					Exp <= LExp;
				END IF; -- END IF EnCompareMan = '1'
			END IF; -- END IF reset = 0
		END IF; -- END IF clk = '1' and clk'event
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: AddSubMan
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    June 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY AddSubMan IS
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		Sign		: IN std_logic;
		AddSub	: IN std_logic;
		Exp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(24 DOWNTO 0);
		SMan		: IN std_logic_vector(24 DOWNTO 0);
		UExp		: OUT std_logic_vector(8 DOWNTO 0); 
		UMan		: OUT std_logic_vector(25 DOWNTO 0);
		RunO		: OUT std_logic);	   
END AddSubMan;
ARCHITECTURE RTL OF AddSubMan IS
BEGIN
	PROCESS (CLK,reset)
		variable NewMan: std_logic_vector(25 DOWNTO 0);	
		variable manA,manB: std_logic_vector(25 DOWNTO 0);	
	BEGIN
		IF (clk = '1' and clk'event) THEN
			IF (reset = '1') THEN
				UExp <= (Others=> '0');
				uMan <= (Others=> '0');
			ELSE
				RunO <= Run;
   				IF (Run = '1') THEN
					manA := '0' & LMan;
					manB := '0' & SMan;
					IF (AddSub = '0') THEN -- We need to add the mantissas
						NewMan := manA + manB; 
					ELSE -- We need to subtract the mantissas 
						NewMan:=manA - manB;
					END IF; -- END IF LSIgn = SSign
					UExp(7 downto 0) <= Exp;
					UMan <= NewMan;
					UExp(8) <= Sign;
				END IF; -- END IF EnAddSubMan = '1'
			END IF; -- END IF reset = 0
		END IF; -- END IF clk = '1' and clk'event
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: Floating Point Adder
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    June 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY Norm1 IS
	PORT(clk		:  IN std_logic;
		reset	:  IN std_logic;
		Run		:  IN std_logic;
 		UMan		:  IN std_logic_vector (25 DOWNTO 0);
		UExp		:  IN std_logic_vector ( 8 DOWNTO 0);
		ExpCor	: OUT std_logic_vector ( 7 DOWNTO 0);
		ShfDst	: OUT std_logic_vector ( 4 DOWNTO 0);
 		OMan		: OUT std_logic_vector (25 DOWNTO 0);
		OExp		: OUT std_logic_vector ( 8 DOWNTO 0);
		RunO		: OUT std_logic);
END Norm1;
ARCHITECTURE RTL OF Norm1 IS
	SIGNAL ExpCorrect : std_logic_vector(7 DOWNTO 0);
	SIGNAL ShiftDistance : std_logic_vector(4 DOWNTO 0);
BEGIN
	PROCESS (CLK,reset)
		--variable exp: std_logic_vector(7 downto 0);	
		--variable manA,manB: std_logic_vector(24 downto 0);	
	BEGIN
		IF (clk = '1' and clk'event) THEN
			IF (reset = '1') THEN
				ExpCorrect <= (OTHERS  => '0');
				ShiftDistance <= (OTHERS  => '0');				
				OMan <= (OTHERS => '0');
				OExp <= (OTHERS => '0');
			ELSE
				RunO <= Run;
				IF (Run = '1') THEN
					--exp := UExp(7 downto 0);
					OMan <= UMan;
					IF (UMan(25) = '1') THEN -- Overflow from Hidden Bits
						ExpCorrect <= "00000001";
						ShiftDistance <= "00000";
						OExp <= UExp;
					ELSIF (UMan(24) = '1') THEN -- No need to adjust exponents
						ExpCorrect <= "00000000";
						ShiftDistance <= "00001";
						OExp <= UExp;
					ELSIF (UMan(23) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111111";
						ShiftDistance <= "00010";
						OExp <= UExp;
					ELSIF (UMan(22) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111110";
						ShiftDistance <= "00011";
						OExp <= UExp;
					ELSIF (UMan(21) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111101";
						ShiftDistance <= "00100";
						OExp <= UExp;
					ELSIF (UMan(20) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111100";
						ShiftDistance <= "00101";
						OExp <= UExp;
					ELSIF (UMan(19) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111011";
						ShiftDistance <= "00110";
						OExp <= UExp;
					ELSIF (UMan(18) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111010";
						ShiftDistance <= "00111";
						OExp <= UExp;
					ELSIF (UMan(17) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111001";
						ShiftDistance <= "01000";
						OExp <= UExp;
					ELSIF (UMan(16) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111000";
						ShiftDistance <= "01001";
						OExp <= UExp;
					ELSIF (UMan(15) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110111";
						ShiftDistance <= "01010";
						OExp <= UExp;
					ELSIF (UMan(14) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110110";
						ShiftDistance <= "01011";
						OExp <= UExp;
					ELSIF (UMan(13) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110101";
						ShiftDistance <= "01100";
						OExp <= UExp;
					ELSIF (UMan(12) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110100";
						ShiftDistance <= "01101";
						OExp <= UExp;
					ELSIF (UMan(11) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110011";
						ShiftDistance <= "01110";
						OExp <= UExp;
					ELSIF (UMan(10) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110010";
						ShiftDistance <= "01111";
						OExp <= UExp;
					ELSIF (UMan(9) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110001";
						ShiftDistance <= "10000";
						OExp <= UExp;
					ELSIF (UMan(8) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110000";
						ShiftDistance <= "10001";
						OExp <= UExp;
					ELSIF (UMan(7) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101111";
						ShiftDistance <= "10010";
						OExp <= UExp;
					ELSIF (UMan(6) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101110";
						ShiftDistance <= "10011";
						OExp <= UExp;
					ELSIF (UMan(5) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101101";
						ShiftDistance <= "10100";
						OExp <= UExp;
					ELSIF (UMan(4) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101100";
						ShiftDistance <= "10101";
						OExp <= UExp;
					ELSIF (UMan(3) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101011";
						ShiftDistance <= "10110";
						OExp <= UExp;
					ELSIF (UMan(2) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101010";
						ShiftDistance <= "10111";
						OExp <= UExp;
					ELSIF (UMan(1) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101010";
						ShiftDistance <= "11000";
						OExp <= UExp;
					ELSE 				  -- Mantissa equals zero
						ExpCorrect <= "00000000";
						ShiftDistance <= "00000";
						OExp <="000000000";
					END IF;
				END IF; -- END Run = '1'
			END IF; -- END IF reset = 0
		END IF; -- END IF clk = '1' and clk'event
	END PROCESS;
	ExpCor <= ExpCorrect;
	ShfDst <= ShiftDistance;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: Floating Point Adder
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    June 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY Norm2 IS
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		ExpCor	: IN std_logic_vector (7 DOWNTO 0);
		ShfDst	: IN std_logic_vector (4 DOWNTO 0);
		UExp		: IN std_logic_vector(8 DOWNTO 0); 
		UMan		: IN std_logic_vector(25 DOWNTO 0);	  
		Q		: OUT std_logic_vector(31 DOWNTO 0);
		RunO		: OUT std_logic);
END Norm2;
ARCHITECTURE RTL OF Norm2 IS
	SIGNAL QQ : std_logic_vector(31 DOWNTO 0);
BEGIN
	PROCESS (CLK,reset)
		variable exp: std_logic_vector(7 downto 0);	
		variable ManOut, ManA: std_logic_vector(25 downto 0);
		variable RoundMan : std_logic_vector(25 downto 0);
		--variable manA,manB: std_logic_vector(24 downto 0);	
	BEGIN
		IF (clk = '1' and clk'event) THEN
			IF (reset = '1') THEN
				QQ <= (Others=> '0');
			ELSE
				RunO <= Run;
				IF (Run = '1') THEN
					exp := UExp(7 DOWNTO 0);
					ManA := Uman;
					exp := exp + ExpCor;
					ManOut := SHL(ManA,ShfDst);
					RoundMan := '0' & ManOut(24 downto 0);
					IF ((RoundMan(1) = '1') AND (RoundMan(2) = '1') ) then  -- Round the Mantissa
					RoundMan := RoundMan + "00000000000000000000000010";
					END IF;
					-- If we round up and produce a carry, we need to add one to the exponent
					IF (RoundMan(25) = '1') then
					exp := exp + 1;
					end if;
					QQ(31) <= UExp(8);
					QQ(30 DOWNTO 23) <= exp;
					QQ(22 downto 0) <= RoundMan(24 downto 2);
				END IF; -- END IF Run = '1'
			END IF; -- END IF reset = 0
		END IF; -- END IF clk = '1' and clk'event
	END PROCESS;
	Q <= QQ;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: Six Stage Floating Point Adder Core
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    November 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_Logic_1164.all;
ENTITY RegStage8 IS
	PORT(Ck		: IN std_logic;
		Reset	: IN std_logic;
		Run		: IN std_logic;
		Datain	: IN std_logic_vector(31 DOWNTO 0);
		Q		: OUT std_logic_vector(31 DOWNTO 0);
		RunO		: OUT std_logic);
END RegStage8;
ARCHITECTURE RTL OF RegStage8 IS
	SIGNAL D : std_logic_vector(31 DOWNTO 0);
	SIGNAL R : std_logic;
BEGIN
	PROCESS
	BEGIN
		WAIT UNTIL ((Ck'EVENT) AND (Ck= '1'));
		IF (Reset = '1') THEN 		 -- Changed Reset to Active High
			D <= "00000000000000000000000000000000";
			R <= '0';
		ELSIF (Run = '1') THEN
			D <= Datain;
			R <= Run;
		ELSE
			D <= D;
			R <= Run;
		END IF;
	END process;
	Q <= D;
	RunO <= R;
END RTL;
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design Name : 8 stage pipelined Floating Point Adder
-- Name		: Ibrahim Sahin & Clay Gloster
-- Date 		: March 2001
-- Description	:
-------------------------------------------------------------
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design Name : 8 stage pipelined Floating Point Adder
-- Name		: Ibrahim Sahin & Clay Gloster
-- Date 		: March 2001
-- Description	:
-------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
ENTITY FpAdderCore_8 IS
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		EnR		: IN std_logic;
		EnL		: IN std_logic;
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		Op_Q		: OUT std_logic_vector(31 DOWNTO 0);
		EnN		: OUT std_logic);
END FpAdderCore_8;
ARCHITECTURE STRUCTURAL OF FpAdderCore_8 IS
COMPONENT CompareExp
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		EnR		: IN std_logic;
		EnL		: IN std_logic;
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		LExp		: OUT std_logic_vector(7 DOWNTO 0);
		SExp		: OUT std_logic_vector(7 DOWNTO 0);
		LMan		: OUT std_logic_vector(22 DOWNTO 0); 
		SMan		: OUT std_logic_vector(22 DOWNTO 0);	   
		LSign	: OUT std_logic;
		SSign	: OUT std_logic;
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT ComputeShift
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		SExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(22 DOWNTO 0);
		SMan		: IN std_logic_vector(22 DOWNTO 0);
		LSign	: IN std_logic;
		SSign	: IN std_logic;
		LExpP	: OUT std_logic_vector(7 DOWNTO 0);
		SExpP	: OUT std_logic_vector(7 DOWNTO 0);
		LManP	: OUT std_logic_vector(22 DOWNTO 0);
		SManP	: OUT std_logic_vector(22 DOWNTO 0);
		LSignP	: OUT std_logic;
		SSignP	: OUT std_logic;
		shiftdistance : OUT std_logic_vector(4 DOWNTO 0);
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT ShiftMan
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		shiftdistance : IN std_logic_vector(4 DOWNTO 0); 
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		SExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(22 DOWNTO 0);
		SMan		: IN std_logic_vector(22 DOWNTO 0);
		LSign	: IN std_logic;
		SSign	: IN std_logic;
		LExpP	: OUT std_logic_vector(7 DOWNTO 0);
		LManP	: OUT std_logic_vector(24 DOWNTO 0);
		SManP	: OUT std_logic_vector(24 DOWNTO 0);
		LSignP	: OUT std_logic;
		SSignP	: OUT std_logic;
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT CompareMan
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		LSign	: IN std_logic;
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(24 DOWNTO 0);
		SSign	: IN std_logic;
		SMan		: IN std_logic_vector(24 DOWNTO 0);
		Exp		: OUT std_logic_vector(7 DOWNTO 0); 
		LMan1	: OUT std_logic_vector(24 DOWNTO 0);	    
		SMan1	: OUT std_logic_vector(24 DOWNTO 0);	    
		Sign		: OUT std_logic;
		AddSub 	: OUT std_logic;
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT AddSubMan
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		Sign		: IN std_logic;
		AddSub	: IN std_logic;
		Exp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(24 DOWNTO 0);
		SMan		: IN std_logic_vector(24 DOWNTO 0);
		UExp		: OUT std_logic_vector(8 DOWNTO 0); 
		UMan		: OUT std_logic_vector(25 DOWNTO 0);
		RunO		: OUT std_logic);	   
END COMPONENT;
COMPONENT Norm1
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
 		UMan		: IN std_logic_vector(25 downto 0);
		UExp		: IN std_logic_vector (8 DOWNTO 0);
		ExpCor	: OUT std_logic_vector (7 DOWNTO 0);
		ShfDst	: OUT std_logic_vector (4 DOWNTO 0);
		OMan		: OUT std_logic_vector (25 DOWNTO 0);
		OExp		: OUT std_logic_vector (8 DOWNTO 0);
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT Norm2
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		ExpCor	: IN std_logic_vector (7 DOWNTO 0);
		ShfDst	: IN std_logic_vector (4 DOWNTO 0);
		UExp		: IN std_logic_vector (8 DOWNTO 0); 
		UMan		: IN std_logic_vector (25 DOWNTO 0);	  
		Q 		: OUT std_logic_vector(31 DOWNTO 0);
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT RegStage8
	PORT(Ck		: IN std_logic;
		Reset	: IN std_logic;
		Run		: IN std_logic;
		Datain	: IN std_logic_vector(31 DOWNTO 0);
		Q		: OUT std_logic_vector(31 DOWNTO 0);
		RunO		: OUT std_logic);
END COMPONENT;
SIGNAL LExp12	: std_logic_vector(7 downto 0);
SIGNAL SExp12	: std_logic_vector(7 downto 0);
SIGNAL LMan12	: std_logic_vector(22 downto 0); 
SIGNAL SMan12	: std_logic_vector(22 downto 0);
SIGNAL LSign12	: std_logic;
SIGNAL SSign12	: std_logic;
SIGNAL RunO12	: std_logic;
SIGNAL LExpP23		: std_logic_vector(7 downto 0);
SIGNAL SExpP23		: std_logic_vector(7 downto 0);
SIGNAL LManP23		: std_logic_vector(22 downto 0);
SIGNAL SManP23		: std_logic_vector(22 downto 0);
SIGNAL LSignP23	: std_logic;
SIGNAL SSignP23	: std_logic;
SIGNAL shiftdistance23 : std_logic_vector(4 downto 0);
SIGNAL RunO23		: std_logic;
SIGNAL LExpP34		: std_logic_vector(7 DOWNTO 0);
SIGNAL LManP34		: std_logic_vector(24 DOWNTO 0);
SIGNAL SManP34		: std_logic_vector(24 DOWNTO 0);
SIGNAL LSignP34	: std_logic;
SIGNAL SSignP34	: std_logic;
SIGNAL RunO34		: std_logic;
SIGNAL Exp45		: std_logic_vector(7 DOWNTO 0); 
SIGNAL LMan145		: std_logic_vector(24 DOWNTO 0);
SIGNAL SMan145		: std_logic_vector(24 DOWNTO 0);
SIGNAL Sign45		: std_logic;
SIGNAL AddSub45 	: std_logic;
SIGNAL RunO45		: std_logic;
SIGNAL UExp56		: std_logic_vector(8 DOWNTO 0); 
SIGNAL UMan56		: std_logic_vector(25 DOWNTO 0);
SIGNAL RunO56		: std_logic;
SIGNAL ExpCor67	: std_logic_vector (7 DOWNTO 0);
SIGNAL ShfDst67	: std_logic_vector (4 DOWNTO 0);
SIGNAL OExp67		: std_logic_vector(8 DOWNTO 0); 
SIGNAL OMan67		: std_logic_vector(25 DOWNTO 0);
SIGNAL RunO67		: std_logic;
SIGNAL Q78 		: std_logic_vector(31 DOWNTO 0);
SIGNAL RunO78		: std_logic;
BEGIN
	Inst1: CompareExp PORT MAP (clk, reset, EnR, EnL, Op_A, Op_B, LExp12, SExp12, LMan12, SMan12, LSign12, SSign12, RunO12);
	Inst2: ComputeShift PORT MAP (clk, reset, RunO12, LExp12, SExp12, LMan12, SMan12, LSign12, SSign12, LExpP23, SExpP23, LManP23, SManP23, LSignP23, SSignP23, shiftdistance23, RunO23);
	Inst3: ShiftMan PORT MAP (clk, reset, RunO23, shiftdistance23, LExpP23, SExpP23, LManP23, SManP23, LSignP23, SSignP23, LExpP34, LManP34, SManP34, LSignP34, SSignP34, RunO34);
	Inst4: CompareMan PORT MAP (clk, reset, RunO34,	LSignP34, LExpP34, LManP34, SSignP34, SManP34, Exp45, LMan145, SMan145, Sign45, AddSub45, RunO45);
	Inst5: AddSubMan PORT MAP (clk ,reset, RunO45, Sign45, AddSub45, Exp45, LMan145, SMan145, UExp56, UMan56, RunO56);
	Inst6: Norm1 PORT MAP (clk, reset, RunO56, UMan56, UExp56, ExpCor67, ShfDst67, OMan67, OExp67, RunO67);
	Inst7: Norm2 PORT MAP (clk, reset, RunO67, ExpCor67, ShfDst67, OExp67, OMan67, Q78, RunO78); 	
	Inst8: RegStage8 PORT MAP (clk, reset, RunO78, Q78, Op_Q, EnN);
END STRUCTURAL;
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design Name : 8 stage pipelined Floating Point Subtractor
-- Name		: Ibrahim Sahin & Clay Gloster
-- Date 		: March 2001
-- Description	:
-------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
ENTITY FpSubCore_8 IS
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		EnR		: IN std_logic;
		EnL		: IN std_logic;
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		Op_Q		: OUT std_logic_vector(31 DOWNTO 0);
		EnN		: OUT std_logic);
END FpSubCore_8;
ARCHITECTURE STRUCTURAL OF FpSubCore_8 IS
COMPONENT SubCompareExp
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		EnR		: IN std_logic;
		EnL		: IN std_logic;
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		LExp		: OUT std_logic_vector(7 DOWNTO 0);
		SExp		: OUT std_logic_vector(7 DOWNTO 0);
		LMan		: OUT std_logic_vector(22 DOWNTO 0); 
		SMan		: OUT std_logic_vector(22 DOWNTO 0);	   
		LSign	: OUT std_logic;
		SSign	: OUT std_logic;
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT ComputeShift
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		SExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(22 DOWNTO 0);
		SMan		: IN std_logic_vector(22 DOWNTO 0);
		LSign	: IN std_logic;
		SSign	: IN std_logic;
		LExpP	: OUT std_logic_vector(7 DOWNTO 0);
		SExpP	: OUT std_logic_vector(7 DOWNTO 0);
		LManP	: OUT std_logic_vector(22 DOWNTO 0);
		SManP	: OUT std_logic_vector(22 DOWNTO 0);
		LSignP	: OUT std_logic;
		SSignP	: OUT std_logic;
		shiftdistance : OUT std_logic_vector(4 DOWNTO 0);
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT ShiftMan
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		shiftdistance : IN std_logic_vector(4 DOWNTO 0); 
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		SExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(22 DOWNTO 0);
		SMan		: IN std_logic_vector(22 DOWNTO 0);
		LSign	: IN std_logic;
		SSign	: IN std_logic;
		LExpP	: OUT std_logic_vector(7 DOWNTO 0);
		LManP	: OUT std_logic_vector(24 DOWNTO 0);
		SManP	: OUT std_logic_vector(24 DOWNTO 0);
		LSignP	: OUT std_logic;
		SSignP	: OUT std_logic;
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT CompareMan
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		LSign	: IN std_logic;
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(24 DOWNTO 0);
		SSign	: IN std_logic;
		SMan		: IN std_logic_vector(24 DOWNTO 0);
		Exp		: OUT std_logic_vector(7 DOWNTO 0); 
		LMan1	: OUT std_logic_vector(24 DOWNTO 0);	    
		SMan1	: OUT std_logic_vector(24 DOWNTO 0);	    
		Sign		: OUT std_logic;
		AddSub 	: OUT std_logic;
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT AddSubMan
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		Sign		: IN std_logic;
		AddSub	: IN std_logic;
		Exp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(24 DOWNTO 0);
		SMan		: IN std_logic_vector(24 DOWNTO 0);
		UExp		: OUT std_logic_vector(8 DOWNTO 0); 
		UMan		: OUT std_logic_vector(25 DOWNTO 0);
		RunO		: OUT std_logic);	   
END COMPONENT;
COMPONENT Norm1
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
 		UMan		: IN std_logic_vector(25 downto 0);
		UExp		: IN std_logic_vector (8 DOWNTO 0);
		ExpCor	: OUT std_logic_vector (7 DOWNTO 0);
		ShfDst	: OUT std_logic_vector (4 DOWNTO 0);
		OMan		: OUT std_logic_vector (25 DOWNTO 0);
		OExp		: OUT std_logic_vector (8 DOWNTO 0);
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT Norm2
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Run		: IN std_logic;
		ExpCor	: IN std_logic_vector (7 DOWNTO 0);
		ShfDst	: IN std_logic_vector (4 DOWNTO 0);
		UExp		: IN std_logic_vector (8 DOWNTO 0); 
		UMan		: IN std_logic_vector (25 DOWNTO 0);	  
		Q 		: OUT std_logic_vector(31 DOWNTO 0);
		RunO		: OUT std_logic);
END COMPONENT;
COMPONENT RegStage8
	PORT(Ck		: IN std_logic;
		Reset	: IN std_logic;
		Run		: IN std_logic;
		Datain	: IN std_logic_vector(31 DOWNTO 0);
		Q		: OUT std_logic_vector(31 DOWNTO 0);
		RunO		: OUT std_logic);
END COMPONENT;
SIGNAL LExp12	: std_logic_vector(7 downto 0);
SIGNAL SExp12	: std_logic_vector(7 downto 0);
SIGNAL LMan12	: std_logic_vector(22 downto 0); 
SIGNAL SMan12	: std_logic_vector(22 downto 0);
SIGNAL LSign12	: std_logic;
SIGNAL SSign12	: std_logic;
SIGNAL RunO12	: std_logic;
SIGNAL LExpP23		: std_logic_vector(7 downto 0);
SIGNAL SExpP23		: std_logic_vector(7 downto 0);
SIGNAL LManP23		: std_logic_vector(22 downto 0);
SIGNAL SManP23		: std_logic_vector(22 downto 0);
SIGNAL LSignP23	: std_logic;
SIGNAL SSignP23	: std_logic;
SIGNAL shiftdistance23 : std_logic_vector(4 downto 0);
SIGNAL RunO23		: std_logic;
SIGNAL LExpP34		: std_logic_vector(7 DOWNTO 0);
SIGNAL LManP34		: std_logic_vector(24 DOWNTO 0);
SIGNAL SManP34		: std_logic_vector(24 DOWNTO 0);
SIGNAL LSignP34	: std_logic;
SIGNAL SSignP34	: std_logic;
SIGNAL RunO34		: std_logic;
SIGNAL Exp45		: std_logic_vector(7 DOWNTO 0); 
SIGNAL LMan45		: std_logic_vector(24 DOWNTO 0);
SIGNAL SMan45		: std_logic_vector(24 DOWNTO 0);
SIGNAL Sign45		: std_logic;
SIGNAL AddSub45 	: std_logic;
SIGNAL RunO45		: std_logic;
SIGNAL UExp56		: std_logic_vector(8 DOWNTO 0); 
SIGNAL UMan56		: std_logic_vector(25 DOWNTO 0);
SIGNAL RunO56		: std_logic;
SIGNAL ExpCor67	: std_logic_vector (7 DOWNTO 0);
SIGNAL ShfDst67	: std_logic_vector (4 DOWNTO 0);
SIGNAL OExp67		: std_logic_vector(8 DOWNTO 0); 
SIGNAL OMan67		: std_logic_vector(25 DOWNTO 0);
SIGNAL RunO67		: std_logic;
SIGNAL Q78 		: std_logic_vector(31 DOWNTO 0);
SIGNAL RunO78		: std_logic;
BEGIN
	Inst1: SubCompareExp PORT MAP (clk, reset, EnR, EnL, Op_A, Op_B, LExp12, SExp12, LMan12, SMan12, LSign12, SSign12, RunO12);
	Inst2: ComputeShift PORT MAP (clk, reset, RunO12, LExp12, SExp12, LMan12, SMan12, LSign12, SSign12, LExpP23, SExpP23, LManP23, SManP23, LSignP23, SSignP23, shiftdistance23, RunO23);
	Inst3: ShiftMan PORT MAP (clk, reset, RunO23, shiftdistance23, LExpP23, SExpP23, LManP23, SManP23, LSignP23, SSignP23, LExpP34, LManP34, SManP34, LSignP34, SSignP34, RunO34);
	Inst4: CompareMan PORT MAP (clk, reset, RunO34,	LSignP34, LExpP34, LManP34, SSignP34, SManP34, Exp45, LMan45, SMan45, Sign45, AddSub45, RunO45);
	Inst5: AddSubMan PORT MAP (clk ,reset, RunO45, Sign45, AddSub45, Exp45, LMan45, SMan45, UExp56, UMan56, RunO56);
	Inst6: Norm1 PORT MAP (clk, reset, RunO56, UMan56, UExp56, ExpCor67, ShfDst67, OMan67, OExp67, RunO67);
	Inst7: Norm2 PORT MAP (clk, reset, RunO67, ExpCor67, ShfDst67, OExp67, OMan67, Q78, RunO78); 	
	Inst8: RegStage8 PORT MAP (clk, reset, RunO78, Q78, Op_Q, EnN);
END STRUCTURAL;