-------------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design:  control_unit for accumulator
-- Name:   Clay Gloster and Rosie Dickens
--
-- Date:   Spring 2001
-- Description:  This unit is essentially an FSM
--
--
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_Logic_1164.all;
ENTITY acc_control_unit IS
      PORT (	CLK		: in std_logic;
		RESET	 	: in std_logic;
		ENABLE		: in std_logic;
		EMPTY		: in std_logic;
		ADDERDONE   	: in std_logic;
		ENABLEADDER	: out std_logic;
		LoadR1,LoadR2,LoadR3,LoadR4			: out std_logic;
		LoadR5,LoadR6,LoadR7,LoadR8			: out std_logic; 
		CTL		: out std_logic_vector (2 downto 0);
		DONE		: out std_logic);
END acc_control_unit;
ARCHITECTURE RTL of acc_control_unit IS
   type StateType is (Idle,S0,S1,S2,
Empty0,Empty1,Empty2,Empty3,Empty4,Empty5,Empty6,Empty7,
Empty10,Empty11,Empty12,Empty13,Empty14,Empty15,Empty16,Empty17,
Empty20,Empty21,Empty22,Empty23,Empty24,Empty25,Empty26,Empty27,
Empty30,Empty31,Empty32,Empty33,Empty34,Empty35,Empty36,Empty37,
Empty40,Empty41,Empty42,Empty43,Empty44,Empty45,Empty46,Empty47,
Empty50,Empty51,Empty52,Empty53,Empty54,Empty55,Empty56,Empty57,
Empty60,Empty61,Empty62,Empty63,Empty64,Empty65,Empty66,Empty67
);
   signal CurrentState: StateType;
begin
   FSM_1: process 
   begin
wait until clk' EVENT and clk = '1'; --WAIT FOR RISING clk EDGE
-- ININTIALIZATION
   if (Reset = '1') then
        CurrentState<= Idle;                     
   else 
         case (CurrentState) is 
            when Idle=>			--machine is now ready to accept inputs
   		if (EMPTY = '0') then	     			
            		CurrentState <= Idle;
		else     			
            		CurrentState <= Empty0;    -- Got an empty signal 
		end if;	
	    when Empty0=>	-- Empty the pipe
            	CurrentState <= Empty1;	
            when Empty1=>	-- Empty the pipe
            	CurrentState <= Empty2;	
	    when Empty2=>	-- Empty the pipe
            	CurrentState <= Empty3;	
            when Empty3=>	-- Empty the pipe
            	CurrentState <= Empty4;	
	    when Empty4=>	-- Empty the pipe
            	CurrentState <= Empty5;	
            when Empty5=>	-- Empty the pipe
            	CurrentState <= Empty6;	
	    when Empty6=>	-- Empty the pipe
            	CurrentState <= Empty7;	
            when Empty7=>	-- Empty the pipe
            	CurrentState <= Empty10;	
            when Empty10=>	-- ADD R1+R2
            	CurrentState <= Empty11;	
            when Empty11=>	-- ADD R3+R4
            	CurrentState <= Empty12;	
	    when Empty12=>	-- ADD R5+R6
            	CurrentState <= Empty13;	
            when Empty13=>	-- ADD R7+R8
            	CurrentState <= Empty14;	
	    when Empty14=>	-- Empty the pipe
            	CurrentState <= Empty15;	
            when Empty15=>	-- Empty the pipe
            	CurrentState <= Empty16;	
	    when Empty16=>	-- Empty the pipe
            	CurrentState <= Empty17;	
            when Empty17=>	-- Empty the pipe
            	CurrentState <= Empty20;	
	    when Empty20=>	-- Empty the pipe
            	CurrentState <= Empty21;	
            when Empty21=>	-- Empty the pipe
            	CurrentState <= Empty22;	
	    when Empty22=>	-- Empty the pipe
            	CurrentState <= Empty23;	
            when Empty23=>	-- Empty the pipe
            	CurrentState <= Empty24;	
	    when Empty24=>	-- Empty the pipe
            	CurrentState <= Empty25;	
            when Empty25=>	-- Empty the pipe
            	CurrentState <= Empty26;	
	    when Empty26=>	-- Empty the pipe
            	CurrentState <= Empty27;	
            when Empty27=>	-- Empty the pipe
            	CurrentState <= Empty30;	
            when Empty30=>	-- ADD R1+R2
            	CurrentState <= Empty31;	
            when Empty31=>	-- ADD R3+R4
            	CurrentState <= Empty32;	
	    when Empty32=>	-- 
            	CurrentState <= Empty33;	
            when Empty33=>	--
            	CurrentState <= Empty34;	
	    when Empty34=>	-- Empty the pipe
            	CurrentState <= Empty35;	
            when Empty35=>	-- Empty the pipe
            	CurrentState <= Empty36;	
	    when Empty36=>	-- Empty the pipe
            	CurrentState <= Empty37;	
            when Empty37=>	-- Empty the pipe
            	CurrentState <= Empty40;
	    when Empty40=>	-- Empty the pipe
            	CurrentState <= Empty41;	
            when Empty41=>	-- Empty the pipe
            	CurrentState <= Empty42;	
	    when Empty42=>	-- Empty the pipe
            	CurrentState <= Empty43;	
            when Empty43=>	-- Empty the pipe
            	CurrentState <= Empty44;	
	    when Empty44=>	-- Empty the pipe
            	CurrentState <= Empty45;	
            when Empty45=>	-- Empty the pipe
            	CurrentState <= Empty46;	
	    when Empty46=>	-- Empty the pipe
            	CurrentState <= Empty47;	
            when Empty47=>	-- Empty the pipe
            	CurrentState <= Empty50;	
            when Empty50=>	-- ADD R1+R2
            	CurrentState <= Empty51;	
            when Empty51=>
            	CurrentState <= Empty52;	
	    when Empty52=>	-- 
            	CurrentState <= Empty53;	
            when Empty53=>	--
            	CurrentState <= Empty54;	
	    when Empty54=>	-- Empty the pipe
            	CurrentState <= Empty55;	
            when Empty55=>	-- Empty the pipe
            	CurrentState <= Empty56;	
	    when Empty56=>	-- Empty the pipe
            	CurrentState <= Empty57;	
            when Empty57=>	-- Empty the pipe
            	CurrentState <= Empty60;
	    when Empty60=>	-- Empty the pipe
            	CurrentState <= Empty61;	
            when Empty61=>	-- Empty the pipe
            	CurrentState <= Idle;	
            when others =>
               CurrentState <= Idle;
         end case;
   end if;
   end process FSM_1;
 	outputlogic: process (CurrentState,ENABLE,EMPTY,ADDERDONE)
   begin
	case (CurrentState) is
	when Idle=>   	--machine is now ready to accept inputs  
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "001"; -- Op_Q + Op_A
		DONE <= '0';
		if (ENABLE = '1') AND (EMPTY = '0') then	     			
            		ENABLEADDER <= '1';
		else	     			
            		ENABLEADDER <= '0';
		end if;	
	when Empty0=>     
		LoadR1 <= '1';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty1=>     
		LoadR1 <= '0';
		LoadR2 <= '1';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty2=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '1';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty3=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '1';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty4=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '1';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty5=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '1';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty6=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '1';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty7=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '1';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';	
	when Empty10=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "010";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty11=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "011";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty12=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "100";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty13=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "101";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty14=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty15=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty16=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty17=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty20=>     
		LoadR1 <= '1';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty21=>     
		LoadR1 <= '0';
		LoadR2 <= '1';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty22=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '1';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty23=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '1';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty24=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '1';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty25=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '1';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty26=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '1';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty27=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '1';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';	
	when Empty30=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "010";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty31=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "011";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty32=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty33=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty34=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty35=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty36=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty37=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty40=>     
		LoadR1 <= '1';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty41=>     
		LoadR1 <= '0';
		LoadR2 <= '1';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty42=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '1';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty43=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '1';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty44=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '1';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty45=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '1';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty46=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '1';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty47=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '1';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';	
	when Empty50=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "010";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty51=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty52=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty53=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty54=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty55=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty56=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty57=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty60=>     
		LoadR1 <= '1';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
		ENABLEADDER <= '1';
	when Empty61=>     
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '1';
		ENABLEADDER <= '0';
	when others =>
		ENABLEADDER <= '0';
		LoadR1 <= '0';
		LoadR2 <= '0';
		LoadR3 <= '0';
		LoadR4 <= '0';
		LoadR5 <= '0';
		LoadR6 <= '0';
		LoadR7 <= '0';
		LoadR8 <= '0';
		CTL <= "000";
		DONE <= '0';
	end case;      
end process outputlogic;
end RTL;
-------------------------------------------------------------------
--Copyright 2001 by Howard University All rights reserved.
--
--Design:  Register
--Name: Clay Gloster
--
--Date:  June 2001
--Description:
--
--
--
-------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_Logic_1164.all;
ENTITY reg32 IS
	PORT(Datain	: IN std_logic_vector(31 DOWNTO 0);
		Load		: IN std_logic;
		Ck		: IN std_logic;
		Reset	: IN std_logic;
		Q		: OUT std_logic_vector(31 DOWNTO 0));
END reg32;
ARCHITECTURE RTL OF reg32 IS
	SIGNAL D : std_logic_vector(31 DOWNTO 0);
BEGIN
	PROCESS
	BEGIN
		WAIT UNTIL ((Ck'EVENT) AND (Ck= '1'));
		IF (Reset = '1') THEN 		 -- Changed Reset to Active High
			D <= "00000000000000000000000000000000";
		ELSIF (Load = '1') THEN
			D <= Datain;
		ELSE
			D <= D;
		END IF;
	END process;
	Q <= D;
END RTL;
-------------------------------------------------------------------
--Copyright 2001 by Howard University All rights reserved.
--
--Design:  The Input Selector Function for an Accumulator
--Name: E. Rose Dickens
--
--Date: June 2001
--Description:  Non-Generic Module
--Inputs include Op_A and Op_Q and Registers whose input will be
--32 bit numbers  
--CTL of this function is a 3 bit number
--Input Selector Function is represented as a MUX
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY InputSelector IS
	Port(CTL: in std_logic_vector (2 downto 0); -- accepts 3 bit numbers
	      Op_A: in std_logic_vector (31 downto 0);
	      Op_Q: in std_logic_vector (31 downto 0); --also an output of the fp_adder
	      R1: in std_logic_vector (31 downto 0);
	      R2: in std_logic_vector (31 downto 0);
	      R3: in std_logic_vector (31 downto 0);
	      R4: in std_logic_vector (31 downto 0);
	      R5: in std_logic_vector (31 downto 0);
	      R6: in std_logic_vector (31 downto 0);
	      R7: in std_logic_vector (31 downto 0);
	      R8: in std_logic_vector (31 downto 0);
	      CoreLEFT: out std_logic_vector (31 downto 0);
	      CoreRIGHT: out std_logic_vector (31 downto 0));
END;
ARCHITECTURE COND_DATA_FLOW OF InputSelector IS
BEGIN
    PROCESS (CTL, Op_A, Op_Q, R1, R2, R3, R4, R5, R6, R7, R8)
    BEGIN
	CASE CTL IS
		when "000" =>
		   CoreLEFT  <= "00000000000000000000000000000000";
		   CoreRIGHT <= "00000000000000000000000000000000";
		when "001" =>
		   CoreLEFT  <= Op_Q;
		   CoreRIGHT <= Op_A;
		when "010" =>
		   CoreLEFT  <= R1;
		   CoreRIGHT <= R2;
		when "011" =>
		   CoreLEFT  <= R3;
		   CoreRIGHT <= R4;
		when "100" =>
		   CoreLEFT  <= R5;
		   CoreRIGHT <= R6;
		when "101" =>
		   CoreLEFT  <= R7;
		   CoreRIGHT <= R8;
		when others =>
		   CoreLEFT  <="--------------------------------";
		   CoreRIGHT <="--------------------------------";
	END CASE;
    END PROCESS;
END COND_DATA_FLOW;
-------------------------------------------------------------------
-- Copyright 2001 by NC State University All rights reserved.
--
-- Design: Floating Point Accumulator Data Unit
-- Name:    Clay Gloster
--	
-- Date:    June 2001
-- Description:
--  Pipelined.
-------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY acc_data_unit IS
	PORT(	clk	: IN std_logic;
		reset	: IN std_logic;
		Op_A	: IN std_logic_vector(31 DOWNTO 0);
		LoadR1,LoadR2,LoadR3,LoadR4			: IN std_logic;
		LoadR5,LoadR6,LoadR7,LoadR8			: IN std_logic;  
		Enable 	: IN std_logic;
		CTL	: IN std_logic_vector (2 downto 0);
	        EnN     : OUT std_logic;	 
		Op_Q	: OUT std_logic_vector(31 DOWNTO 0));
END acc_data_unit;
ARCHITECTURE STRUCTURAL OF acc_data_unit IS
component FpAdderCore_8_hold 
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Enable		: IN std_logic;
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		Op_Q		: OUT std_logic_vector(31 DOWNTO 0);
		Done		: OUT std_logic);
END component;
COMPONENT reg32
	PORT(Datain	: IN std_logic_vector(31 DOWNTO 0);
		Load		: IN std_logic;
		Ck		: IN std_logic;
		Reset	: IN std_logic;
		Q		: OUT std_logic_vector(31 DOWNTO 0));
END COMPONENT; 
COMPONENT InputSelector
	Port(CTL: in std_logic_vector (2 downto 0); -- accepts 3 bit numbers
	      Op_A: in std_logic_vector (31 downto 0);
	      Op_Q: in std_logic_vector (31 downto 0); --also an output of the fp_adder
	      R1: in std_logic_vector (31 downto 0);
	      R2: in std_logic_vector (31 downto 0);
	      R3: in std_logic_vector (31 downto 0);
	      R4: in std_logic_vector (31 downto 0);
	      R5: in std_logic_vector (31 downto 0);
	      R6: in std_logic_vector (31 downto 0);
	      R7: in std_logic_vector (31 downto 0);
	      R8: in std_logic_vector (31 downto 0);
	      CoreLEFT: out std_logic_vector (31 downto 0);
	      CoreRIGHT: out std_logic_vector (31 downto 0));
END COMPONENT; 
SIGNAL CoreLEFT, CoreRIGHT : std_logic_vector(31 DOWNTO 0);
SIGNAL R1,R2,R3,R4,R5,R6,R7,R8 : std_logic_vector (31 downto 0);
SIGNAL sOp_Q : std_logic_vector (31 downto 0);
BEGIN
	InstR1: reg32
		PORT MAP (sOp_Q,LoadR1,clk,reset,R1);
	InstR2: reg32
		PORT MAP (sOp_Q,LoadR2,clk,reset,R2);
	InstR3: reg32
		PORT MAP (sOp_Q,LoadR3,clk,reset,R3);
	InstR4: reg32
		PORT MAP (sOp_Q,LoadR4,clk,reset,R4);
	InstR5: reg32
		PORT MAP (sOp_Q,LoadR5,clk,reset,R5);
	InstR6: reg32
		PORT MAP (sOp_Q,LoadR6,clk,reset,R6);
	InstR7: reg32
		PORT MAP (sOp_Q,LoadR7,clk,reset,R7);
	InstR8: reg32
		PORT MAP (sOp_Q,LoadR8,clk,reset,R8);
	Instadder: FpAdderCore_8_hold 
		PORT MAP (clk, reset, Enable, CoreLEFT, CoreRIGHT, sOp_Q, EnN);
	InstMUX: InputSelector 
		port map (CTL,Op_A,sOp_Q,R1,R2,R3,R4,R5,R6,R7,R8,CoreLEFT,CoreRIGHT);
Op_Q <= R1;
END STRUCTURAL;
-------------------------------------------------------------------
--Copyright 2001 by Howard University All rights reserved.
--
--Design: Accumulator Core
--Name: E. Rose Dickens
--
--Date: June 2001
--Description: The inputs on the accumulator will include Op_A,
--Enable, and Empty
-------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY acc_core IS
	PORT(clk		: IN std_logic;
		reset		: IN std_logic;
		Op_A		: IN std_logic_vector (31 downto 0);
		ENABLE	: IN std_logic;
		EMPTY		: IN std_logic;
		Op_Q		: OUT std_logic_vector (31 downto 0);
		DONE		: OUT std_logic);
END acc_core;
ARCHITECTURE STRUCTURAL OF acc_core IS
COMPONENT acc_control_unit
	PORT (CLK		: in std_logic;
		RESET	 	: in std_logic;
		ENABLE	: in std_logic;
		EMPTY		: in std_logic;
		ADDERDONE   	: in std_logic;
		ENABLEADDER	: out std_logic;
		LoadR1,LoadR2,LoadR3,LoadR4			: out std_logic;
		LoadR5,LoadR6,LoadR7,LoadR8			: out std_logic; 
		CTL		: out std_logic_vector (2 downto 0);
		DONE		: out std_logic);
END COMPONENT;
COMPONENT acc_data_unit 
	PORT(clk		: IN std_logic;
		reset		: IN std_logic;
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		LoadR1,LoadR2,LoadR3,LoadR4			: IN std_logic;
		LoadR5,LoadR6,LoadR7,LoadR8			: IN std_logic;  
		Enable 	: IN std_logic;
		CTL	: IN std_logic_vector (2 downto 0);
	        	EnN     	: OUT std_logic;	 
		Op_Q	: OUT std_logic_vector(31 DOWNTO 0));
END COMPONENT;
SIGNAL ADDERDONE		: std_logic;
SIGNAL ENABLEADDER		: std_logic;
SIGNAL LOADR1		: std_logic;
SIGNAL LOADR2		: std_logic;
SIGNAL LOADR3		: std_logic;
SIGNAL LOADR4		: std_logic;
SIGNAL LOADR5		: std_logic;
SIGNAL LOADR6		: std_logic;
SIGNAL LOADR7		: std_logic;
SIGNAL LOADR8		: std_logic;
SIGNAL CTL		: std_logic_vector (2 downto 0);
BEGIN
	Inst_control: acc_control_unit PORT MAP (clk, reset, ENABLE, EMPTY, ADDERDONE,			        
			  ENABLEADDER, LOADR1, LOADR2, LOADR3, LOADR4, LOADR5,
		        LOADR6, LOADR7, LOADR8, CTL, DONE);
	Inst_data: acc_data_unit PORT MAP (CLK, RESET, Op_A, LOADR1, LOADR2, LOADR3, 		   
		     LOADR4, LOADR5, LOADR6, LOADR7, LOADR8, ENABLEADDER, CTL, ADDERDONE, Op_Q);
END STRUCTURAL;