--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design Name : 8 stage pipelined Floating Point Adder and 8 stage 
--			Floating point Subtractor Core (See bottom of file)
-- This Core holds the data in each stage until the enable is asserted.
-- Name		: Ibrahim Sahin & Clay Gloster
-- Date 		: September 2001
-- Description	:
--------------------------------------------------------------
-----------------PARTS IN THE ADDER---------------------------
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: SubCompareExp_comb
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    October 1999
-- Description: This is the first stage of the subtractor, it complements the 
-- Sign Bit.
-- Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
ENTITY SubCompareExp_comb IS
	PORT(
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		LExp		: OUT std_logic_vector(7 DOWNTO 0);
		SExp		: OUT std_logic_vector(7 DOWNTO 0);
		LMan		: OUT std_logic_vector(22 DOWNTO 0); 
		SMan		: OUT std_logic_vector(22 DOWNTO 0);	   
		LSign	: OUT std_logic;
		SSign	: OUT std_logic);
END SubCompareExp_comb;
ARCHITECTURE RTL OF SubCompareExp_comb IS
BEGIN
	PROCESS (Op_A,Op_B)
		variable expA,expB: std_logic_vector(8 DOWNTO 0);
	BEGIN
					expA := '0' & Op_A(30 DOWNTO 23);
					expB := '0' & Op_B(30 DOWNTO 23);
					IF (expA > expB) THEN
						IF (Op_B(30 DOWNTO 0) = "0000000000000000000000000000000") THEN
							SSign <= '0';
						ELSE
							SSign <= not Op_B(31);
						END IF;
						SExp <=  Op_B(30 DOWNTO 23);
						SMan <= Op_B(22 DOWNTO 0);
						LSign <= Op_A(31);
						LExp <= Op_A(30 DOWNTO 23);
						LMan <= Op_A(22 DOWNTO 0);
					ELSE
						SSign <= Op_A(31);
						SExp <=  Op_A(30 DOWNTO 23);
						SMan <= Op_A(22 DOWNTO 0);
						IF (Op_B(30 DOWNTO 0) = "0000000000000000000000000000000") THEN
							LSign <= '0';
						ELSE				
							LSign <= not Op_B(31);
						END IF;
						LExp <= Op_B(30 DOWNTO 23);
						LMan <= Op_B(22 DOWNTO 0);
					END IF;
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: CompareExp_comb
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    October 1999
-- Description: This is the first stage of the adder core
-- Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
ENTITY CompareExp_comb IS
	PORT(
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		LExp		: OUT std_logic_vector(7 DOWNTO 0);
		SExp		: OUT std_logic_vector(7 DOWNTO 0);
		LMan		: OUT std_logic_vector(22 DOWNTO 0); 
		SMan		: OUT std_logic_vector(22 DOWNTO 0);	   
		LSign	: OUT std_logic;
		SSign	: OUT std_logic);
END CompareExp_comb;
ARCHITECTURE RTL OF CompareExp_comb IS
BEGIN
	PROCESS (Op_A,Op_B)
		variable expA,expB: std_logic_vector(8 DOWNTO 0);
	BEGIN
					expA := '0' & Op_A(30 DOWNTO 23);
					expB := '0' & Op_B(30 DOWNTO 23);
					IF (expA > expB) THEN
						SSign <= Op_B(31);
						SExp <=  Op_B(30 DOWNTO 23);
						SMan <= Op_B(22 DOWNTO 0);
						LSign <= Op_A(31);
						LExp <= Op_A(30 DOWNTO 23);
						LMan <= Op_A(22 DOWNTO 0);
					ELSE
						SSign <= Op_A(31);
						SExp <=  Op_A(30 DOWNTO 23);
						SMan <= Op_A(22 DOWNTO 0);
						LSign <= Op_B(31);
						LExp <= Op_B(30 DOWNTO 23);
						LMan <= Op_B(22 DOWNTO 0);
					END IF;
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: ComputeShift_comb
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    October 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHR;
use IEEE.std_logic_unsigned.CONV_INTEGER;
use IEEE.std_logic_misc.OR_REDUCE;
use IEEE.std_logic_arith.all;
ENTITY ComputeShift_comb IS
	PORT(
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		SExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(22 DOWNTO 0);
		SMan		: IN std_logic_vector(22 DOWNTO 0);
		LSign	: IN std_logic;
		SSign	: IN std_logic;
		LExpP	: OUT std_logic_vector(7 DOWNTO 0);
		SExpP	: OUT std_logic_vector(7 DOWNTO 0);
		LManP	: OUT std_logic_vector(22 DOWNTO 0);
		SManP	: OUT std_logic_vector(22 DOWNTO 0);
		LSignP	: OUT std_logic;
		SSignP	: OUT std_logic;
		shiftdistance : OUT std_logic_vector(4 DOWNTO 0));
END ComputeShift_comb;
ARCHITECTURE RTL OF ComputeShift_comb IS
BEGIN
	PROCESS (LExp,SExp,LMan,SMan,LSign,SSign)
		variable sdistance: std_logic_vector(7 DOWNTO 0);
	BEGIN
					sdistance := LExp - SExp;
					LExpP <= LExp;
					SExpP<= SExp;
					LManP <= LMan;
					SManP<=SMan;
					LSignP <= LSign;
					SSignP <= SSign;
					shiftdistance <= sdistance(4 DOWNTO 0);
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: ShiftMan_comb
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    October 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHR;
use IEEE.std_logic_unsigned.CONV_INTEGER;
use IEEE.std_logic_misc.OR_REDUCE;
use IEEE.std_logic_arith.all;
ENTITY ShiftMan_comb IS
	PORT(
		shiftdistance : IN std_logic_vector(4 DOWNTO 0); 
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		SExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(22 DOWNTO 0);
		SMan		: IN std_logic_vector(22 DOWNTO 0);
		LSign	: IN std_logic;
		SSign	: IN std_logic;
		LExpP	: OUT std_logic_vector(7 DOWNTO 0);
		LManP	: OUT std_logic_vector(23 DOWNTO 0);
		SManP	: OUT std_logic_vector(23 DOWNTO 0);
		LSignP	: OUT std_logic;
		SSignP	: OUT std_logic);
END ShiftMan_comb;
ARCHITECTURE RTL OF ShiftMan_comb IS
BEGIN
	PROCESS (shiftdistance,LExp,SExp,LMan,SMan,LSign,SSign)
		variable manA,manB: std_logic_vector(23 DOWNTO 0);    
		variable bitA,bitB: std_logic;
	BEGIN
					-- Add Hidden Bits to Manitissas
					bitA := LSign OR OR_REDUCE(LMan) OR OR_REDUCE(LExp);
					manA := bitA&LMan(22 downto 0);
					bitB := SSign OR OR_REDUCE(SMan) OR OR_REDUCE(SExp);
					manB := bitB&SMan(22 downto 0);
					SManP <= SHR(manB,shiftdistance);
					LExpP <= LExp;
					LManP <= manA;
					LSignP <= LSign;
					SSignP <= SSign;
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: CompareMan_comb
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    November 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY CompareMan_comb IS
	PORT(
		LSign	: IN std_logic;
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(23 DOWNTO 0);
		SSign	: IN std_logic;
		SMan		: IN std_logic_vector(23 DOWNTO 0);
		Exp		: OUT std_logic_vector(7 DOWNTO 0); 
		LMan1	: OUT std_logic_vector(23 DOWNTO 0);	    
		SMan1	: OUT std_logic_vector(23 DOWNTO 0);	    
		Sign		: OUT std_logic;
		AddSub 	: OUT std_logic);
END CompareMan_comb;
ARCHITECTURE RTL OF CompareMan_comb IS
BEGIN
	PROCESS (LSign,LExp,LMan,SSign,SMan)
	BEGIN
					IF (LSign = SSign) THEN -- Signs of the two numbers are the same
						Sign <= LSign;
						LMan1 <= LMan;
						SMan1 <= SMan;
						AddSub <= '0';
					ELSE -- Signs are different
						IF (LMan > SMan) THEN
							Sign <= LSign;
							AddSub <= '1';
							LMan1 <= LMan;
							SMan1 <= SMan;
						ELSE
							Sign <= SSign;
							AddSub <= '1';
							LMan1 <= SMan;
							SMan1 <= LMan;
						END IF;
					END IF; -- END IF LSIgn = SSign
					Exp <= LExp;
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: AddSubMan_comb
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    June 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY AddSubMan_comb IS
	PORT(
		Sign		: IN std_logic;
		AddSub	: IN std_logic;
		Exp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(23 DOWNTO 0);
		SMan		: IN std_logic_vector(23 DOWNTO 0);
		UExp		: OUT std_logic_vector(8 DOWNTO 0); 
		UMan		: OUT std_logic_vector(24 DOWNTO 0));	   
END AddSubMan_comb;
ARCHITECTURE RTL OF AddSubMan_comb IS
BEGIN
	PROCESS (Sign,AddSub,Exp,LMan,SMan)
		variable NewMan: std_logic_vector(24 DOWNTO 0);	
		variable manA,manB: std_logic_vector(24 DOWNTO 0);	
	BEGIN
					manA := '0' & LMan;
					manB := '0' & SMan;
					IF (AddSub = '0') THEN -- We need to add the mantissas
						NewMan := manA + manB; 
					ELSE -- We need to subtract the mantissas 
						NewMan:=manA - manB;
					END IF; -- END IF LSIgn = SSign
					UExp(7 downto 0) <= Exp;
					UMan <= NewMan;
					UExp(8) <= Sign;
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: Floating Point Adder
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    June 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY Norm1_comb IS
	PORT(
 		UMan		:  IN std_logic_vector (24 DOWNTO 0);
		UExp		:  IN std_logic_vector ( 8 DOWNTO 0);
		ExpCor	: OUT std_logic_vector ( 7 DOWNTO 0);
		ShfDst	: OUT std_logic_vector ( 4 DOWNTO 0);
 		OMan		: OUT std_logic_vector (24 DOWNTO 0);
		OExp		: OUT std_logic_vector ( 8 DOWNTO 0));
END Norm1_comb;
ARCHITECTURE RTL OF Norm1_comb IS
	SIGNAL ExpCorrect : std_logic_vector(7 DOWNTO 0);
	SIGNAL ShiftDistance : std_logic_vector(4 DOWNTO 0);
BEGIN
	PROCESS (UMan,UExp)
		--variable exp: std_logic_vector(7 downto 0);	
		--variable manA,manB: std_logic_vector(24 downto 0);	
	BEGIN
					--exp := UExp(7 downto 0);
					OMan <= UMan;
					IF (UMan(24) = '1') THEN -- Overflow from Hidden Bits
						ExpCorrect <= "00000001";
						ShiftDistance <= "00000";
						OExp <= UExp;
					ELSIF (UMan(23) = '1') THEN -- No need to adjust exponents
						ExpCorrect <= "00000000";
						ShiftDistance <= "00001";
						OExp <= UExp;
					ELSIF (UMan(22) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111111";
						ShiftDistance <= "00010";
						OExp <= UExp;
					ELSIF (UMan(21) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111110";
						ShiftDistance <= "00011";
						OExp <= UExp;
					ELSIF (UMan(20) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111101";
						ShiftDistance <= "00100";
						OExp <= UExp;
					ELSIF (UMan(19) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111100";
						ShiftDistance <= "00101";
						OExp <= UExp;
					ELSIF (UMan(18) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111011";
						ShiftDistance <= "00110";
						OExp <= UExp;
					ELSIF (UMan(17) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111010";
						ShiftDistance <= "00111";
						OExp <= UExp;
					ELSIF (UMan(16) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111001";
						ShiftDistance <= "01000";
						OExp <= UExp;
					ELSIF (UMan(15) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11111000";
						ShiftDistance <= "01001";
						OExp <= UExp;
					ELSIF (UMan(14) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110111";
						ShiftDistance <= "01010";
						OExp <= UExp;
					ELSIF (UMan(13) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110110";
						ShiftDistance <= "01011";
						OExp <= UExp;
					ELSIF (UMan(12) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110101";
						ShiftDistance <= "01100";
						OExp <= UExp;
					ELSIF (UMan(11) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110100";
						ShiftDistance <= "01101";
						OExp <= UExp;
					ELSIF (UMan(10) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110011";
						ShiftDistance <= "01110";
						OExp <= UExp;
					ELSIF (UMan(9) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110010";
						ShiftDistance <= "01111";
						OExp <= UExp;
					ELSIF (UMan(8) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110001";
						ShiftDistance <= "10000";
						OExp <= UExp;
					ELSIF (UMan(7) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11110000";
						ShiftDistance <= "10001";
						OExp <= UExp;
					ELSIF (UMan(6) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101111";
						ShiftDistance <= "10010";
						OExp <= UExp;
					ELSIF (UMan(5) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101110";
						ShiftDistance <= "10011";
						OExp <= UExp;
					ELSIF (UMan(4) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101101";
						ShiftDistance <= "10100";
						OExp <= UExp;
					ELSIF (UMan(3) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101100";
						ShiftDistance <= "10101";
						OExp <= UExp;
					ELSIF (UMan(2) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101011";
						ShiftDistance <= "10110";
						OExp <= UExp;
					ELSIF (UMan(1) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101010";
						ShiftDistance <= "10111";
						OExp <= UExp;
					ELSIF (UMan(0) = '1') THEN -- We need to adjust down
						ExpCorrect <= "11101010";
						ShiftDistance <= "11000";
						OExp <= UExp;
					ELSE 				  -- Mantissa equals zero
						ExpCorrect <= "00000000";
						ShiftDistance <= "00000";
						OExp <="000000000";
					END IF;
	END PROCESS;
	ExpCor <= ExpCorrect;
	ShfDst <= ShiftDistance;
END RTL;
--------------------------------------------------------------
-- Copyright 1999 by Howard University All rights reserved.
--
-- Design: Floating Point Adder
-- Name:    Clay Gloster & Ibrahim Sahin
--	
-- Date:    June 1999
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY Norm2_comb IS
	PORT(
		ExpCor	: IN std_logic_vector (7 DOWNTO 0);
		ShfDst	: IN std_logic_vector (4 DOWNTO 0);
		UExp		: IN std_logic_vector(8 DOWNTO 0); 
		UMan		: IN std_logic_vector(24 DOWNTO 0);	  
		Q		: OUT std_logic_vector(31 DOWNTO 0));
END Norm2_comb;
ARCHITECTURE RTL OF Norm2_comb IS
	SIGNAL QQ : std_logic_vector(31 DOWNTO 0);
BEGIN
	PROCESS (ExpCor,ShfDst,UExp,UMan)
		variable exp: std_logic_vector(7 downto 0);	
		variable ManOut, ManA: std_logic_vector(23 downto 0);
		variable RoundMan : std_logic_vector(22 downto 0);
		--variable manA,manB: std_logic_vector(24 downto 0);	
	BEGIN
					exp := UExp(7 DOWNTO 0);
					ManA := Uman (23 DOWNTO 0);
					QQ(31) <= UExp(8);
					QQ(30 DOWNTO 23) <= exp + ExpCor;
					ManOut := SHL(ManA,ShfDst);
					RoundMan := ManOut(23 downto 1);
					IF (ManOut(1) = '1' AND ManOut(0) = '1' ) then  -- Round the Mantissa
					RoundMan := RoundMan + "00000000000000000000001";
					END IF;
					QQ(22 downto 0) <= RoundMan;
	END PROCESS;
	Q <= QQ;
END RTL;
---------------------------------------------------------------
--Copyright 2001 by Howard University All rights reserved.
--
--Design: Generic Register
--Name: Clay Gloster
--
--Date: May 2001
--Description:  Generic Register
--Width equal to one
--Does not have parallel
---------------------------------------------------------------
library IEEE;
use IEEE.STD_Logic_1164.all;
entity REG_GENERIC_ENABLE is
generic (Width : integer);
port (Datain : in std_logic_vector(Width-1 downto 0);
Clk,Reset,Enable : in std_logic;
Q: out std_logic_vector(Width-1 downto 0) );
end REG_GENERIC_ENABLE;
architecture RTL of REG_GENERIC_ENABLE is
signal D: std_logic_vector(Width-1 downto 0);
begin
start: process(Clk)
variable i: integer;
begin
if (Clk'EVENT and Clk = '1') then
 if (Reset = '1') then  -- Changed Reset to Active High
  for i in 0 to Width-1 loop
   D(i) <= '0';
  end loop;
 elsif (Enable = '1') then
   D <= Datain;
 else
   D <= D;
 end if; -- End if Reset = '1'
end if; -- End if Clk'Event and Clk = '1'
end process;
Q <= D;
end RTL;
---------------------------------------------------------------
--Copyright 2001 by Howard University All rights reserved.
--
--Design: DFF 1bit with Enable
--Name: Clay Gloster
--
--Date: May 2001
--Description:  Generic Register
--Width equal to one
--Does not have parallel
---------------------------------------------------------------
library IEEE;
use IEEE.STD_Logic_1164.all;
entity REG_1bit_ENABLE is
port (Datain : in std_logic;
Clk,Reset,Enable : in std_logic;
Q: out std_logic);
end REG_1bit_ENABLE;
architecture RTL of REG_1bit_ENABLE is
signal D: std_logic;
begin
start: process(Clk)
variable i: integer;
begin
if (Clk'EVENT and Clk = '1') then
 if (Reset = '1') then  -- Changed Reset to Active High
   D <= '0'; 
 elsif (Enable = '1') then
   D <= Datain;
 else
   D <= D;
 end if; -- End if Reset = '1'
end if; -- End if Clk'Event and Clk = '1'
end process;
Q <= D;
end RTL;
---------------------------------------------------------------
--Copyright 2001 by Howard University All rights reserved.
--
--Design: Shift Register
--Name: Clay Gloster
--
--Date: October 2001
--Description:
--
--
---------------------------------------------------------------
library IEEE;
use IEEE.STD_Logic_1164.all;
entity shiftregister is
generic (Width : integer);
port (Datain : in std_logic;
Clk,Reset,Enable : in std_logic;
Q: out std_logic);
end shiftregister;
architecture structural of shiftregister is
component REG_1bit_ENABLE
  port (Datain : in std_logic;
        Clk,Reset,Enable: in std_logic;
        Q: out std_logic);
end component;
signal REGIO : std_logic_vector(0 to Width);
begin
 lpp1: for i in  0 to Width-1 generate
 I0:   REG_1bit_ENABLE 
       port map ( REGIO(i), Clk, Reset, Enable, REGIO(i+1) );
       end generate;
 REGIO(0) <= Datain;
 Q <= REGIO(Width);
end structural;
---------------------------------------------------------------
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design Name : 8 stage pipelined Floating Point Adder
-- Name		: Ibrahim Sahin & Clay Gloster
-- Date 		: March 2001
-- Description	:
-------------------------------------------------------------
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design Name : 8 stage pipelined Floating Point Adder
-- Name		: Ibrahim Sahin & Clay Gloster
-- Date 		: March 2001
-- Description	:
-------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
ENTITY FpAdderCore_8_hold IS
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Enable		: IN std_logic;
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		Op_Q		: OUT std_logic_vector(31 DOWNTO 0);
		Done		: OUT std_logic);
END FpAdderCore_8_hold;
ARCHITECTURE STRUCTURAL OF FpAdderCore_8_hold IS
COMPONENT CompareExp_comb
	PORT(
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		LExp		: OUT std_logic_vector(7 DOWNTO 0);
		SExp		: OUT std_logic_vector(7 DOWNTO 0);
		LMan		: OUT std_logic_vector(22 DOWNTO 0); 
		SMan		: OUT std_logic_vector(22 DOWNTO 0);	   
		LSign	: OUT std_logic;
		SSign	: OUT std_logic);
END COMPONENT;
COMPONENT ComputeShift_comb
	PORT(
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		SExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(22 DOWNTO 0);
		SMan		: IN std_logic_vector(22 DOWNTO 0);
		LSign	: IN std_logic;
		SSign	: IN std_logic;
		LExpP	: OUT std_logic_vector(7 DOWNTO 0);
		SExpP	: OUT std_logic_vector(7 DOWNTO 0);
		LManP	: OUT std_logic_vector(22 DOWNTO 0);
		SManP	: OUT std_logic_vector(22 DOWNTO 0);
		LSignP	: OUT std_logic;
		SSignP	: OUT std_logic;
		shiftdistance : OUT std_logic_vector(4 DOWNTO 0));
END COMPONENT;
COMPONENT ShiftMan_comb
	PORT(
		shiftdistance : IN std_logic_vector(4 DOWNTO 0); 
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		SExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(22 DOWNTO 0);
		SMan		: IN std_logic_vector(22 DOWNTO 0);
		LSign	: IN std_logic;
		SSign	: IN std_logic;
		LExpP	: OUT std_logic_vector(7 DOWNTO 0);
		LManP	: OUT std_logic_vector(23 DOWNTO 0);
		SManP	: OUT std_logic_vector(23 DOWNTO 0);
		LSignP	: OUT std_logic;
		SSignP	: OUT std_logic);
END COMPONENT;
COMPONENT CompareMan_comb
	PORT(
		LSign	: IN std_logic;
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(23 DOWNTO 0);
		SSign	: IN std_logic;
		SMan		: IN std_logic_vector(23 DOWNTO 0);
		Exp		: OUT std_logic_vector(7 DOWNTO 0); 
		LMan1	: OUT std_logic_vector(23 DOWNTO 0);	    
		SMan1	: OUT std_logic_vector(23 DOWNTO 0);	    
		Sign		: OUT std_logic;
		AddSub 	: OUT std_logic);
END COMPONENT;
COMPONENT AddSubMan_comb
	PORT(
		Sign		: IN std_logic;
		AddSub	: IN std_logic;
		Exp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(23 DOWNTO 0);
		SMan		: IN std_logic_vector(23 DOWNTO 0);
		UExp		: OUT std_logic_vector(8 DOWNTO 0); 
		UMan		: OUT std_logic_vector(24 DOWNTO 0));	   
END COMPONENT;
COMPONENT Norm1_comb
	PORT(
 		UMan		: IN std_logic_vector(24 downto 0);
		UExp		: IN std_logic_vector (8 DOWNTO 0);
		ExpCor	: OUT std_logic_vector (7 DOWNTO 0);
		ShfDst	: OUT std_logic_vector (4 DOWNTO 0);
		OMan		: OUT std_logic_vector (24 DOWNTO 0);
		OExp		: OUT std_logic_vector (8 DOWNTO 0));
END COMPONENT;
COMPONENT Norm2_comb
	PORT(
		ExpCor	: IN std_logic_vector (7 DOWNTO 0);
		ShfDst	: IN std_logic_vector (4 DOWNTO 0);
		UExp		: IN std_logic_vector (8 DOWNTO 0); 
		UMan		: IN std_logic_vector (24 DOWNTO 0);	  
		Q 		: OUT std_logic_vector(31 DOWNTO 0));
END COMPONENT;
COMPONENT REG_GENERIC_ENABLE
generic (Width : integer);
port (Datain : in std_logic_vector(Width-1 downto 0);
Clk,Reset,Enable : in std_logic;
Q: out std_logic_vector(Width-1 downto 0) );
END COMPONENT;
COMPONENT REG_1bit_ENABLE
port (Datain : in std_logic;
Clk,Reset,Enable : in std_logic;
Q: out std_logic);
end COMPONENT;
COMPONENT shiftregister
generic (Width : integer);
port (Datain : in std_logic;
Clk,Reset,Enable : in std_logic;
Q: out std_logic);
end COMPONENT;
SIGNAL LExp12, LExp12_o		: std_logic_vector(7 downto 0);
SIGNAL SExp12, SExp12_o		: std_logic_vector(7 downto 0);
SIGNAL LMan12, LMan12_o		: std_logic_vector(22 downto 0); 
SIGNAL SMan12, SMan12_o		: std_logic_vector(22 downto 0);
SIGNAL LSign12, LSign12_o 	: std_logic;
SIGNAL SSign12, SSign12_o 	: std_logic;
SIGNAL LExp23,LExp23_o			: std_logic_vector(7 downto 0);
SIGNAL SExp23,SExp23_o			: std_logic_vector(7 downto 0);
SIGNAL LMan23,LMan23_o			: std_logic_vector(22 downto 0);
SIGNAL SMan23,SMan23_o			: std_logic_vector(22 downto 0);
SIGNAL LSign23,LSign23_o		: std_logic;
SIGNAL SSign23,SSign23_o		: std_logic;
SIGNAL sdistance23,sdistance23_o	: std_logic_vector(4 downto 0);
SIGNAL LExp34,LExp34_o		: std_logic_vector(7 DOWNTO 0);
SIGNAL LMan34,LMan34_o		: std_logic_vector(23 DOWNTO 0);
SIGNAL SMan34,SMan34_o		: std_logic_vector(23 DOWNTO 0);
SIGNAL LSign34,LSign34_o	: std_logic;
SIGNAL SSign34,SSign34_o	: std_logic;
SIGNAL Exp45,Exp45_o		: std_logic_vector(7 DOWNTO 0); 
SIGNAL LMan45,LMan45_o		: std_logic_vector(23 DOWNTO 0);
SIGNAL SMan45,SMan45_o		: std_logic_vector(23 DOWNTO 0);
SIGNAL Sign45,Sign45_o		: std_logic;
SIGNAL AddSub45,AddSub45_o 	: std_logic;
SIGNAL UExp56,UExp56_o		: std_logic_vector(8 DOWNTO 0); 
SIGNAL UMan56,UMan56_o		: std_logic_vector(24 DOWNTO 0);
SIGNAL ExpCor67,ExpCor67_o	: std_logic_vector (7 DOWNTO 0);
SIGNAL ShfDst67,ShfDst67_o	: std_logic_vector (4 DOWNTO 0);
SIGNAL OExp67,OExp67_o		: std_logic_vector(8 DOWNTO 0); 
SIGNAL OMan67,OMan67_o		: std_logic_vector(24 DOWNTO 0);
SIGNAL Q78,Q78_o 		: std_logic_vector(31 DOWNTO 0);
BEGIN
-- Stage 1
	Inst1: CompareExp_comb PORT MAP (Op_A, Op_B, LExp12, SExp12, LMan12, SMan12, LSign12, SSign12);
	InstR1: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(LExp12,Clk,Reset,Enable,LExp12_o);
	InstR2: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(SExp12,Clk,Reset,Enable,SExp12_o);
	InstR3: REG_GENERIC_ENABLE 
	GENERIC MAP(23)
	PORT MAP(LMan12,Clk,Reset,Enable,LMan12_o);
	InstR4: REG_GENERIC_ENABLE 
	GENERIC MAP(23)
	PORT MAP(SMan12,Clk,Reset,Enable,SMan12_o);
	InstR5: REG_1bit_ENABLE 
	PORT MAP(SSign12,Clk,Reset,Enable,SSign12_o);
	InstR6: REG_1bit_ENABLE 
	PORT MAP(LSign12,Clk,Reset,Enable,LSign12_o);
-- Stage 2
	Inst2: ComputeShift_comb PORT MAP (LExp12_o, SExp12_o, LMan12_o, SMan12_o, LSign12_o, SSign12_o, LExp23, SExp23, LMan23, SMan23, LSign23, SSign23, sdistance23);
	InstR7: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(LExp23,Clk,Reset,Enable,LExp23_o);
	InstR8: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(SExp23,Clk,Reset,Enable,SExp23_o);
	InstR9: REG_GENERIC_ENABLE 
	GENERIC MAP(23)
	PORT MAP(LMan23,Clk,Reset,Enable,LMan23_o);
	InstR10: REG_GENERIC_ENABLE 
	GENERIC MAP(23)
	PORT MAP(SMan23,Clk,Reset,Enable,SMan23_o);
	InstR11: REG_1bit_ENABLE 
	PORT MAP(SSign23,Clk,Reset,Enable,SSign23_o);
	InstR12: REG_1bit_ENABLE 
	PORT MAP(LSign23,Clk,Reset,Enable,LSign23_o);
	InstR13: REG_GENERIC_ENABLE 
	GENERIC MAP(5)
	PORT MAP(sdistance23,Clk,Reset,Enable,sdistance23_o);
--Stage 3
	Inst3: ShiftMan_comb PORT MAP (sdistance23_o, LExp23_o, SExp23_o, LMan23_o, SMan23_o, LSign23_o, SSign23_o, LExp34, LMan34, SMan34, LSign34, SSign34);
	InstR14: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(LExp34,Clk,Reset,Enable,LExp34_o);
	InstR15: REG_GENERIC_ENABLE 
	GENERIC MAP(24)
	PORT MAP(LMan34,Clk,Reset,Enable,LMan34_o);
	InstR16: REG_GENERIC_ENABLE 
	GENERIC MAP(24)
	PORT MAP(SMan34,Clk,Reset,Enable,SMan34_o);
	InstR17: REG_1bit_ENABLE 
	PORT MAP(SSign34,Clk,Reset,Enable,SSign34_o);
	InstR18: REG_1bit_ENABLE 
	PORT MAP(LSign34,Clk,Reset,Enable,LSign34_o);
--Stage 4
	Inst4: CompareMan_comb PORT MAP (LSign34_o, LExp34_o, LMan34_o, SSign34_o, SMan34_o, Exp45, LMan45, SMan45, Sign45, AddSub45);
	InstR19: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(Exp45,Clk,Reset,Enable,Exp45_o);
	InstR20: REG_GENERIC_ENABLE 
	GENERIC MAP(24)
	PORT MAP(LMan45,Clk,Reset,Enable,LMan45_o);
	InstR21: REG_GENERIC_ENABLE 
	GENERIC MAP(24)
	PORT MAP(SMan45,Clk,Reset,Enable,SMan45_o);
	InstR22: REG_1bit_ENABLE 
	PORT MAP(Sign45,Clk,Reset,Enable,Sign45_o);
	InstR23: REG_1bit_ENABLE 
	PORT MAP(AddSub45,Clk,Reset,Enable,AddSub45_o);
--Stage 5
	Inst5: AddSubMan_comb PORT MAP (Sign45_o, AddSub45_o, Exp45_o, LMan45_o, SMan45_o, UExp56, UMan56);
	InstR24: REG_GENERIC_ENABLE 
	GENERIC MAP(9)
	PORT MAP(UExp56,Clk,Reset,Enable,UExp56_o);
	InstR25: REG_GENERIC_ENABLE 
	GENERIC MAP(25)
	PORT MAP(UMan56,Clk,Reset,Enable,UMan56_o);
--Stage 6
	Inst6: Norm1_comb PORT MAP (UMan56_o, UExp56_o, ExpCor67, ShfDst67, OMan67, OExp67);
	InstR26: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(ExpCor67,Clk,Reset,Enable,ExpCor67_o);
	InstR27: REG_GENERIC_ENABLE 
	GENERIC MAP(5)
	PORT MAP(ShfDst67,Clk,Reset,Enable,ShfDst67_o);
	InstR28: REG_GENERIC_ENABLE 
	GENERIC MAP(25)
	PORT MAP(OMan67,Clk,Reset,Enable,OMan67_o);
	InstR29: REG_GENERIC_ENABLE 
	GENERIC MAP(9)
	PORT MAP(OExp67,Clk,Reset,Enable,OExp67_o);
--Stage 7
	Inst7: Norm2_comb PORT MAP (ExpCor67_o, ShfDst67_o, OExp67_o, OMan67_o, Q78);
	InstR30: REG_GENERIC_ENABLE 
	GENERIC MAP(32)
	PORT MAP(Q78,Clk,Reset,Enable,Q78_o);
--Stage 8
	InstR31: REG_GENERIC_ENABLE 
	GENERIC MAP(32)
	PORT MAP(Q78_o,Clk,Reset,Enable,Op_Q);
-- Shiftregister with Enable
	InstSR: shiftregister
	generic map (8)
	port map (Enable,Clk,Reset,Enable,Done);
END STRUCTURAL;
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design Name : 8 stage pipelined Floating Point Subtractor
-- Name		: Ibrahim Sahin & Clay Gloster
-- Date 		: March 2001
-- Description	:
-------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
ENTITY FpSubCore_8_hold IS
	PORT(clk		: IN std_logic;
		reset	: IN std_logic;
		Enable		: IN std_logic;
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		Op_Q		: OUT std_logic_vector(31 DOWNTO 0);
		Done		: OUT std_logic);
END FpSubCore_8_hold;
ARCHITECTURE STRUCTURAL OF FpSubCore_8_hold IS
COMPONENT SubCompareExp_comb
	PORT(
		Op_A		: IN std_logic_vector(31 DOWNTO 0);
		Op_B		: IN std_logic_vector(31 DOWNTO 0);
		LExp		: OUT std_logic_vector(7 DOWNTO 0);
		SExp		: OUT std_logic_vector(7 DOWNTO 0);
		LMan		: OUT std_logic_vector(22 DOWNTO 0); 
		SMan		: OUT std_logic_vector(22 DOWNTO 0);	   
		LSign	: OUT std_logic;
		SSign	: OUT std_logic);
END COMPONENT;
COMPONENT ComputeShift_comb
	PORT(
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		SExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(22 DOWNTO 0);
		SMan		: IN std_logic_vector(22 DOWNTO 0);
		LSign	: IN std_logic;
		SSign	: IN std_logic;
		LExpP	: OUT std_logic_vector(7 DOWNTO 0);
		SExpP	: OUT std_logic_vector(7 DOWNTO 0);
		LManP	: OUT std_logic_vector(22 DOWNTO 0);
		SManP	: OUT std_logic_vector(22 DOWNTO 0);
		LSignP	: OUT std_logic;
		SSignP	: OUT std_logic;
		shiftdistance : OUT std_logic_vector(4 DOWNTO 0));
END COMPONENT;
COMPONENT ShiftMan_comb
	PORT(
		shiftdistance : IN std_logic_vector(4 DOWNTO 0); 
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		SExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(22 DOWNTO 0);
		SMan		: IN std_logic_vector(22 DOWNTO 0);
		LSign	: IN std_logic;
		SSign	: IN std_logic;
		LExpP	: OUT std_logic_vector(7 DOWNTO 0);
		LManP	: OUT std_logic_vector(23 DOWNTO 0);
		SManP	: OUT std_logic_vector(23 DOWNTO 0);
		LSignP	: OUT std_logic;
		SSignP	: OUT std_logic);
END COMPONENT;
COMPONENT CompareMan_comb
	PORT(
		LSign	: IN std_logic;
		LExp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(23 DOWNTO 0);
		SSign	: IN std_logic;
		SMan		: IN std_logic_vector(23 DOWNTO 0);
		Exp		: OUT std_logic_vector(7 DOWNTO 0); 
		LMan1	: OUT std_logic_vector(23 DOWNTO 0);	    
		SMan1	: OUT std_logic_vector(23 DOWNTO 0);	    
		Sign		: OUT std_logic;
		AddSub 	: OUT std_logic);
END COMPONENT;
COMPONENT AddSubMan_comb
	PORT(
		Sign		: IN std_logic;
		AddSub	: IN std_logic;
		Exp		: IN std_logic_vector(7 DOWNTO 0);
		LMan		: IN std_logic_vector(23 DOWNTO 0);
		SMan		: IN std_logic_vector(23 DOWNTO 0);
		UExp		: OUT std_logic_vector(8 DOWNTO 0); 
		UMan		: OUT std_logic_vector(24 DOWNTO 0));	   
END COMPONENT;
COMPONENT Norm1_comb
	PORT(
 		UMan		: IN std_logic_vector(24 downto 0);
		UExp		: IN std_logic_vector (8 DOWNTO 0);
		ExpCor	: OUT std_logic_vector (7 DOWNTO 0);
		ShfDst	: OUT std_logic_vector (4 DOWNTO 0);
		OMan		: OUT std_logic_vector (24 DOWNTO 0);
		OExp		: OUT std_logic_vector (8 DOWNTO 0));
END COMPONENT;
COMPONENT Norm2_comb
	PORT(
		ExpCor	: IN std_logic_vector (7 DOWNTO 0);
		ShfDst	: IN std_logic_vector (4 DOWNTO 0);
		UExp		: IN std_logic_vector (8 DOWNTO 0); 
		UMan		: IN std_logic_vector (24 DOWNTO 0);	  
		Q 		: OUT std_logic_vector(31 DOWNTO 0));
END COMPONENT;
COMPONENT REG_GENERIC_ENABLE
generic (Width : integer);
port (Datain : in std_logic_vector(Width-1 downto 0);
Clk,Reset,Enable : in std_logic;
Q: out std_logic_vector(Width-1 downto 0) );
END COMPONENT;
COMPONENT REG_1bit_ENABLE
port (Datain : in std_logic;
Clk,Reset,Enable : in std_logic;
Q: out std_logic);
end COMPONENT;
COMPONENT shiftregister
generic (Width : integer);
port (Datain : in std_logic;
Clk,Reset,Enable : in std_logic;
Q: out std_logic);
end COMPONENT;
SIGNAL LExp12, LExp12_o		: std_logic_vector(7 downto 0);
SIGNAL SExp12, SExp12_o		: std_logic_vector(7 downto 0);
SIGNAL LMan12, LMan12_o		: std_logic_vector(22 downto 0); 
SIGNAL SMan12, SMan12_o		: std_logic_vector(22 downto 0);
SIGNAL LSign12, LSign12_o 	: std_logic;
SIGNAL SSign12, SSign12_o 	: std_logic;
SIGNAL LExp23,LExp23_o			: std_logic_vector(7 downto 0);
SIGNAL SExp23,SExp23_o			: std_logic_vector(7 downto 0);
SIGNAL LMan23,LMan23_o			: std_logic_vector(22 downto 0);
SIGNAL SMan23,SMan23_o			: std_logic_vector(22 downto 0);
SIGNAL LSign23,LSign23_o		: std_logic;
SIGNAL SSign23,SSign23_o		: std_logic;
SIGNAL sdistance23,sdistance23_o	: std_logic_vector(4 downto 0);
SIGNAL LExp34,LExp34_o		: std_logic_vector(7 DOWNTO 0);
SIGNAL LMan34,LMan34_o		: std_logic_vector(23 DOWNTO 0);
SIGNAL SMan34,SMan34_o		: std_logic_vector(23 DOWNTO 0);
SIGNAL LSign34,LSign34_o	: std_logic;
SIGNAL SSign34,SSign34_o	: std_logic;
SIGNAL Exp45,Exp45_o		: std_logic_vector(7 DOWNTO 0); 
SIGNAL LMan45,LMan45_o		: std_logic_vector(23 DOWNTO 0);
SIGNAL SMan45,SMan45_o		: std_logic_vector(23 DOWNTO 0);
SIGNAL Sign45,Sign45_o		: std_logic;
SIGNAL AddSub45,AddSub45_o 	: std_logic;
SIGNAL UExp56,UExp56_o		: std_logic_vector(8 DOWNTO 0); 
SIGNAL UMan56,UMan56_o		: std_logic_vector(24 DOWNTO 0);
SIGNAL ExpCor67,ExpCor67_o	: std_logic_vector (7 DOWNTO 0);
SIGNAL ShfDst67,ShfDst67_o	: std_logic_vector (4 DOWNTO 0);
SIGNAL OExp67,OExp67_o		: std_logic_vector(8 DOWNTO 0); 
SIGNAL OMan67,OMan67_o		: std_logic_vector(24 DOWNTO 0);
SIGNAL Q78,Q78_o 		: std_logic_vector(31 DOWNTO 0);
BEGIN
-- Stage 1
	Inst1: SubCompareExp_comb PORT MAP (Op_A, Op_B, LExp12, SExp12, LMan12, SMan12, LSign12, SSign12);
	InstR1: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(LExp12,Clk,Reset,Enable,LExp12_o);
	InstR2: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(SExp12,Clk,Reset,Enable,SExp12_o);
	InstR3: REG_GENERIC_ENABLE 
	GENERIC MAP(23)
	PORT MAP(LMan12,Clk,Reset,Enable,LMan12_o);
	InstR4: REG_GENERIC_ENABLE 
	GENERIC MAP(23)
	PORT MAP(SMan12,Clk,Reset,Enable,SMan12_o);
	InstR5: REG_1bit_ENABLE 
	PORT MAP(SSign12,Clk,Reset,Enable,SSign12_o);
	InstR6: REG_1bit_ENABLE 
	PORT MAP(LSign12,Clk,Reset,Enable,LSign12_o);
-- Stage 2
	Inst2: ComputeShift_comb PORT MAP (LExp12_o, SExp12_o, LMan12_o, SMan12_o, LSign12_o, SSign12_o, LExp23, SExp23, LMan23, SMan23, LSign23, SSign23, sdistance23);
	InstR7: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(LExp23,Clk,Reset,Enable,LExp23_o);
	InstR8: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(SExp23,Clk,Reset,Enable,SExp23_o);
	InstR9: REG_GENERIC_ENABLE 
	GENERIC MAP(23)
	PORT MAP(LMan23,Clk,Reset,Enable,LMan23_o);
	InstR10: REG_GENERIC_ENABLE 
	GENERIC MAP(23)
	PORT MAP(SMan23,Clk,Reset,Enable,SMan23_o);
	InstR11: REG_1bit_ENABLE 
	PORT MAP(SSign23,Clk,Reset,Enable,SSign23_o);
	InstR12: REG_1bit_ENABLE 
	PORT MAP(LSign23,Clk,Reset,Enable,LSign23_o);
	InstR13: REG_GENERIC_ENABLE 
	GENERIC MAP(5)
	PORT MAP(sdistance23,Clk,Reset,Enable,sdistance23_o);
--Stage 3
	Inst3: ShiftMan_comb PORT MAP (sdistance23_o, LExp23_o, SExp23_o, LMan23_o, SMan23_o, LSign23_o, SSign23_o, LExp34, LMan34, SMan34, LSign34, SSign34);
	InstR14: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(LExp34,Clk,Reset,Enable,LExp34_o);
	InstR15: REG_GENERIC_ENABLE 
	GENERIC MAP(24)
	PORT MAP(LMan34,Clk,Reset,Enable,LMan34_o);
	InstR16: REG_GENERIC_ENABLE 
	GENERIC MAP(24)
	PORT MAP(SMan34,Clk,Reset,Enable,SMan34_o);
	InstR17: REG_1bit_ENABLE 
	PORT MAP(SSign34,Clk,Reset,Enable,SSign34_o);
	InstR18: REG_1bit_ENABLE 
	PORT MAP(LSign34,Clk,Reset,Enable,LSign34_o);
--Stage 4
	Inst4: CompareMan_comb PORT MAP (LSign34_o, LExp34_o, LMan34_o, SSign34_o, SMan34_o, Exp45, LMan45, SMan45, Sign45, AddSub45);
	InstR19: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(Exp45,Clk,Reset,Enable,Exp45_o);
	InstR20: REG_GENERIC_ENABLE 
	GENERIC MAP(24)
	PORT MAP(LMan45,Clk,Reset,Enable,LMan45_o);
	InstR21: REG_GENERIC_ENABLE 
	GENERIC MAP(24)
	PORT MAP(SMan45,Clk,Reset,Enable,SMan45_o);
	InstR22: REG_1bit_ENABLE 
	PORT MAP(Sign45,Clk,Reset,Enable,Sign45_o);
	InstR23: REG_1bit_ENABLE 
	PORT MAP(AddSub45,Clk,Reset,Enable,AddSub45_o);
--Stage 5
	Inst5: AddSubMan_comb PORT MAP (Sign45_o, AddSub45_o, Exp45_o, LMan45_o, SMan45_o, UExp56, UMan56);
	InstR24: REG_GENERIC_ENABLE 
	GENERIC MAP(9)
	PORT MAP(UExp56,Clk,Reset,Enable,UExp56_o);
	InstR25: REG_GENERIC_ENABLE 
	GENERIC MAP(25)
	PORT MAP(UMan56,Clk,Reset,Enable,UMan56_o);
--Stage 6
	Inst6: Norm1_comb PORT MAP (UMan56_o, UExp56_o, ExpCor67, ShfDst67, OMan67, OExp67);
	InstR26: REG_GENERIC_ENABLE 
	GENERIC MAP(8)
	PORT MAP(ExpCor67,Clk,Reset,Enable,ExpCor67_o);
	InstR27: REG_GENERIC_ENABLE 
	GENERIC MAP(5)
	PORT MAP(ShfDst67,Clk,Reset,Enable,ShfDst67_o);
	InstR28: REG_GENERIC_ENABLE 
	GENERIC MAP(9)
	PORT MAP(OMan67,Clk,Reset,Enable,OMan67_o);
	InstR29: REG_GENERIC_ENABLE 
	GENERIC MAP(25)
	PORT MAP(OExp67,Clk,Reset,Enable,OExp67_o);
--Stage 7
	Inst7: Norm2_comb PORT MAP (ExpCor67_o, ShfDst67_o, OExp67_o, OMan67_o, Q78);
	InstR30: REG_GENERIC_ENABLE 
	GENERIC MAP(32)
	PORT MAP(Q78,Clk,Reset,Enable,Q78_o);
--Stage 8
	InstR31: REG_GENERIC_ENABLE 
	GENERIC MAP(32)
	PORT MAP(Q78_o,Clk,Reset,Enable,Op_Q);
-- Shiftregister with Enable
	InstSR: shiftregister
	generic map (8)
	port map (Enable,Clk,Reset,Enable,Done);
END STRUCTURAL;