--- library IEEE; --use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all; use IEEE.STD_Logic_1164.all, IEEE.std_logic_arith.all,IEEE.std_logic_unsigned.all; entity FixsignI is port (S: in std_logic; Datain: in std_logic_vector(31 downto 0); Q: out std_logic_vector(31 downto 0)); end FixsignI; architecture RTL of FixsignI is begin process (S,Datain) begin if (S='1') then Q <= Datain; elsif ( (S='0') and (Datain="00000000000000000000000000000000")) then Q <= Datain; else Q(31) <= not Datain(31); Q(30 downto 0) <= Datain(30 downto 0); end if; end process; end RTL; --------------- library IEEE; --use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all; use IEEE.STD_Logic_1164.all, IEEE.std_logic_arith.all,IEEE.std_logic_unsigned.all; entity FixsignR is port (S: in std_logic; Datain: in std_logic_vector(31 downto 0); Q: out std_logic_vector(31 downto 0)); end FixsignR; architecture RTL of FixsignR is begin process (S,Datain) begin if (S='0') then Q <= Datain; elsif ( (S='1') and (Datain="00000000000000000000000000000000")) then Q <= Datain; else Q(31) <= not Datain(31); Q(30 downto 0) <= Datain(30 downto 0); end if; end process; end RTL; -------------------------------------------------------------- library IEEE; --use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all; use IEEE.STD_Logic_1164.all, IEEE.std_logic_arith.all,IEEE.std_logic_unsigned.all; entity Multiplexer is port (S,A,B: in std_logic; Q: out std_logic); end Multiplexer; architecture RTL of Multiplexer is begin process (S,A,B) begin if (S='0') then Q <= A; else Q <= B; end if; end process; end RTL; -------------------------------------------------------------- library IEEE; --use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all; use IEEE.STD_Logic_1164.all, IEEE.std_logic_arith.all,IEEE.std_logic_unsigned.all; entity Inverter is port (A: in std_logic; Q: out std_logic); end Inverter; architecture RTL of Inverter is begin process (A) begin Q<= NOT(A); end process; end RTL; -------------------------------------------------------------- library IEEE; --use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all; use IEEE.STD_Logic_1164.all, IEEE.std_logic_arith.all,IEEE.std_logic_unsigned.all; entity COUNTER10 is port (Clock, Reset, INC: in std_logic; Q: out std_logic_vector(9 downto 0)); end COUNTER10; architecture RTL of COUNTER10 is begin process variable Count_v: unsigned(9 downto 0); begin wait until ( (Clock'EVENT) AND (Clock = '1') ); if (Reset = '1') then Count_v := "0000000000"; elsif (Reset = '0') AND (INC = '1') then Count_v := Count_v + 1; else Count_v := Count_v; end if; Q(0) <= Count_v(0); Q(1) <= Count_v(1); Q(2) <= Count_v(2); Q(3) <= Count_v(3); Q(4) <= Count_v(4); Q(5) <= Count_v(5); Q(6) <= Count_v(6); Q(7) <= Count_v(7); Q(8) <= Count_v(8); Q(9) <= Count_v(9); end process; end RTL; -------------------------------------------------------------- -------------------------------------------------------------- -- Copyright 2001 by Howard University All rights reserved. -- -- Design Name : 8 stage pipelined Floating Point Adder and 8 stage -- Floating point Subtractor Core (See bottom of file) -- Name : Ibrahim Sahin & Clay Gloster -- Date : September 2001 -- Description : -------------------------------------------------------------- -----------------PARTS IN THE ADDER--------------------------- -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: SubCompareExp -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: October 1999 -- Description: This is the first stage of the subtractor, it complements the -- Sign Bit. -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; --use IEEE.std_logic_unsigned.">"; use IEEE.std_logic_arith.all; ENTITY SubCompareExp IS PORT(clk : IN std_logic; reset : IN std_logic; EnR : IN std_logic; EnL : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); LExp : OUT std_logic_vector(7 DOWNTO 0); SExp : OUT std_logic_vector(7 DOWNTO 0); LMan : OUT std_logic_vector(22 DOWNTO 0); SMan : OUT std_logic_vector(22 DOWNTO 0); LSign : OUT std_logic; SSign : OUT std_logic; RunO : OUT std_logic); END SubCompareExp; ARCHITECTURE RTL OF SubCompareExp IS BEGIN PROCESS (CLK,reset) variable expA,expB: std_logic_vector(8 DOWNTO 0); BEGIN IF (clk = '1' and clk'event) THEN IF (reset = '1') THEN LExp <= (Others=> '0'); SExp <= (Others=> '0'); LMan <= (Others=> '0'); SMan <= (Others=> '0'); LSign <= '0'; SSign <= '0'; RunO <= '0'; ELSE RunO <= EnR and EnL; IF (EnR = '1' and EnL = '1') THEN expA := '0' & Op_A(30 DOWNTO 23); expB := '0' & Op_B(30 DOWNTO 23); IF (expA > expB) THEN IF (Op_B(30 DOWNTO 0) = "0000000000000000000000000000000") THEN SSign <= '0'; ELSE SSign <= not Op_B(31); END IF; SExp <= Op_B(30 DOWNTO 23); SMan <= Op_B(22 DOWNTO 0); LSign <= Op_A(31); LExp <= Op_A(30 DOWNTO 23); LMan <= Op_A(22 DOWNTO 0); ELSE SSign <= Op_A(31); SExp <= Op_A(30 DOWNTO 23); SMan <= Op_A(22 DOWNTO 0); IF (Op_B(30 DOWNTO 0) = "0000000000000000000000000000000") THEN LSign <= '0'; ELSE LSign <= not Op_B(31); END IF; LExp <= Op_B(30 DOWNTO 23); LMan <= Op_B(22 DOWNTO 0); END IF; END IF; -- END IF EnCompareExp = '1' END IF; -- END IF reset = 0 END IF; -- END IF clk = '1' and clk'event END PROCESS; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: CompareExp -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: October 1999 -- Description: This is the first stage of the adder core -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; --use IEEE.std_logic_unsigned.">"; use IEEE.std_logic_arith.all; ENTITY CompareExp IS PORT(clk : IN std_logic; reset : IN std_logic; EnR : IN std_logic; EnL : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); LExp : OUT std_logic_vector(7 DOWNTO 0); SExp : OUT std_logic_vector(7 DOWNTO 0); LMan : OUT std_logic_vector(22 DOWNTO 0); SMan : OUT std_logic_vector(22 DOWNTO 0); LSign : OUT std_logic; SSign : OUT std_logic; RunO : OUT std_logic); END CompareExp; ARCHITECTURE RTL OF CompareExp IS BEGIN PROCESS (CLK,reset) variable expA,expB: std_logic_vector(8 DOWNTO 0); BEGIN IF (clk = '1' and clk'event) THEN IF (reset = '1') THEN LExp <= (Others=> '0'); SExp <= (Others=> '0'); LMan <= (Others=> '0'); SMan <= (Others=> '0'); LSign <= '0'; SSign <= '0'; RunO <= '0'; ELSE RunO <= EnR and EnL; IF (EnR = '1' and EnL = '1') THEN expA := '0' & Op_A(30 DOWNTO 23); expB := '0' & Op_B(30 DOWNTO 23); IF (expA > expB) THEN SSign <= Op_B(31); SExp <= Op_B(30 DOWNTO 23); SMan <= Op_B(22 DOWNTO 0); LSign <= Op_A(31); LExp <= Op_A(30 DOWNTO 23); LMan <= Op_A(22 DOWNTO 0); ELSE SSign <= Op_A(31); SExp <= Op_A(30 DOWNTO 23); SMan <= Op_A(22 DOWNTO 0); LSign <= Op_B(31); LExp <= Op_B(30 DOWNTO 23); LMan <= Op_B(22 DOWNTO 0); END IF; END IF; -- END IF EnCompareExp = '1' END IF; -- END IF reset = 0 END IF; -- END IF clk = '1' and clk'event END PROCESS; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: ComputeShift -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: October 1999 -- Description: -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned."-"; use IEEE.std_logic_unsigned.">"; use IEEE.std_logic_unsigned.SHR; use IEEE.std_logic_unsigned.CONV_INTEGER; use IEEE.std_logic_misc.OR_REDUCE; use IEEE.std_logic_arith.all; ENTITY ComputeShift IS PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; LExp : IN std_logic_vector(7 DOWNTO 0); SExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(22 DOWNTO 0); SMan : IN std_logic_vector(22 DOWNTO 0); LSign : IN std_logic; SSign : IN std_logic; LExpP : OUT std_logic_vector(7 DOWNTO 0); SExpP : OUT std_logic_vector(7 DOWNTO 0); LManP : OUT std_logic_vector(22 DOWNTO 0); SManP : OUT std_logic_vector(22 DOWNTO 0); LSignP : OUT std_logic; SSignP : OUT std_logic; shiftdistance : OUT std_logic_vector(4 DOWNTO 0); RunO : OUT std_logic); END ComputeShift; ARCHITECTURE RTL OF ComputeShift IS BEGIN PROCESS (CLK,reset) variable sdistance: std_logic_vector(7 DOWNTO 0); BEGIN IF (clk = '1' and clk'event) THEN IF (reset = '1') THEN LExpP <= (Others=> '0'); SExpP <= (Others=> '0'); LManP <= (Others=> '0'); SManP <= (Others=> '0'); LSignP <= '0'; SSignP <= '0'; shiftdistance <= "00000"; ELSE RunO <= Run; IF (Run = '1') THEN sdistance := LExp - SExp; LExpP <= LExp; SExpP<= SExp; LManP <= LMan; SManP<=SMan; LSignP <= LSign; SSignP <= SSign; shiftdistance <= sdistance(4 DOWNTO 0); END IF; -- END IF EnAlign = '1' END IF; -- END IF reset = 0 END IF; -- END IF clk = '1' and clk'event END PROCESS; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: ShiftMan -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: October 1999 -- Description: -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.">"; use IEEE.std_logic_unsigned.SHR; use IEEE.std_logic_unsigned.CONV_INTEGER; use IEEE.std_logic_misc.OR_REDUCE; use IEEE.std_logic_arith.all; ENTITY ShiftMan IS PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; shiftdistance : IN std_logic_vector(4 DOWNTO 0); LExp : IN std_logic_vector(7 DOWNTO 0); SExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(22 DOWNTO 0); SMan : IN std_logic_vector(22 DOWNTO 0); LSign : IN std_logic; SSign : IN std_logic; LExpP : OUT std_logic_vector(7 DOWNTO 0); LManP : OUT std_logic_vector(24 DOWNTO 0); SManP : OUT std_logic_vector(24 DOWNTO 0); LSignP : OUT std_logic; SSignP : OUT std_logic; RunO : OUT std_logic); END ShiftMan; ARCHITECTURE RTL OF ShiftMan IS BEGIN PROCESS (CLK,reset) variable manA,manB: std_logic_vector(24 DOWNTO 0); variable bitA,bitB: std_logic; BEGIN IF (clk = '1' and clk'event) THEN IF (reset = '1') THEN LExpP <= (Others=> '0'); LManP <= (Others=> '0'); SManP <= (Others=> '0'); LSignP <= '0'; SSignP <= '0'; ELSE RunO <= Run; IF (Run = '1') THEN -- Add Hidden Bits to Manitissas bitA := LSign OR OR_REDUCE(LMan) OR OR_REDUCE(LExp); manA := bitA&LMan(22 downto 0)&'0'; bitB := SSign OR OR_REDUCE(SMan) OR OR_REDUCE(SExp); manB := bitB&SMan(22 downto 0)&'0'; SManP <= SHR(manB,shiftdistance); LExpP <= LExp; LManP <= manA; LSignP <= LSign; SSignP <= SSign; END IF; -- END IF EnShiftMan = '1' END IF; -- END IF reset = 0 END IF; -- END IF clk = '1' and clk'event END PROCESS; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: CompareMan -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: November 1999 -- Description: -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned."+"; use IEEE.std_logic_unsigned."-"; --use IEEE.std_logic_unsigned.">"; use IEEE.std_logic_unsigned.SHL; use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR; ENTITY CompareMan IS PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; LSign : IN std_logic; LExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(24 DOWNTO 0); SSign : IN std_logic; SMan : IN std_logic_vector(24 DOWNTO 0); Exp : OUT std_logic_vector(7 DOWNTO 0); LMan1 : OUT std_logic_vector(24 DOWNTO 0); SMan1 : OUT std_logic_vector(24 DOWNTO 0); Sign : OUT std_logic; AddSub : OUT std_logic; RunO : OUT std_logic); END CompareMan; ARCHITECTURE RTL OF CompareMan IS BEGIN PROCESS (CLK,reset) BEGIN IF (clk = '1' and clk'event) THEN IF (reset = '1') THEN Exp <= (Others=> '0'); LMan1 <= (Others=> '0'); SMan1 <= (Others=> '0'); Sign <= '0'; AddSub <= '0'; ELSE RunO <= Run; IF (Run = '1') THEN IF (LSign = SSign) THEN -- Signs of the two numbers are the same Sign <= LSign; LMan1 <= LMan; SMan1 <= SMan; AddSub <= '0'; ELSE -- Signs are different IF (LMan > SMan) THEN Sign <= LSign; AddSub <= '1'; LMan1 <= LMan; SMan1 <= SMan; ELSE Sign <= SSign; AddSub <= '1'; LMan1 <= SMan; SMan1 <= LMan; END IF; END IF; -- END IF LSIgn = SSign Exp <= LExp; END IF; -- END IF EnCompareMan = '1' END IF; -- END IF reset = 0 END IF; -- END IF clk = '1' and clk'event END PROCESS; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: AddSubMan -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: June 1999 -- Description: -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned."+"; use IEEE.std_logic_unsigned."-"; use IEEE.std_logic_unsigned.">"; use IEEE.std_logic_unsigned.SHL; use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR; ENTITY AddSubMan IS PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; Sign : IN std_logic; AddSub : IN std_logic; Exp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(24 DOWNTO 0); SMan : IN std_logic_vector(24 DOWNTO 0); UExp : OUT std_logic_vector(8 DOWNTO 0); UMan : OUT std_logic_vector(25 DOWNTO 0); RunO : OUT std_logic); END AddSubMan; ARCHITECTURE RTL OF AddSubMan IS BEGIN PROCESS (CLK,reset) variable NewMan: std_logic_vector(25 DOWNTO 0); variable manA,manB: std_logic_vector(25 DOWNTO 0); BEGIN IF (clk = '1' and clk'event) THEN IF (reset = '1') THEN UExp <= (Others=> '0'); uMan <= (Others=> '0'); ELSE RunO <= Run; IF (Run = '1') THEN manA := '0' & LMan; manB := '0' & SMan; IF (AddSub = '0') THEN -- We need to add the mantissas NewMan := manA + manB; ELSE -- We need to subtract the mantissas NewMan:=manA - manB; END IF; -- END IF LSIgn = SSign UExp(7 downto 0) <= Exp; UMan <= NewMan; UExp(8) <= Sign; END IF; -- END IF EnAddSubMan = '1' END IF; -- END IF reset = 0 END IF; -- END IF clk = '1' and clk'event END PROCESS; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: Floating Point Adder -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: June 1999 -- Description: -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned."+"; use IEEE.std_logic_unsigned."-"; use IEEE.std_logic_unsigned.">"; use IEEE.std_logic_unsigned.SHL; use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR; ENTITY Norm1 IS PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; UMan : IN std_logic_vector (25 DOWNTO 0); UExp : IN std_logic_vector ( 8 DOWNTO 0); ExpCor : OUT std_logic_vector ( 7 DOWNTO 0); ShfDst : OUT std_logic_vector ( 4 DOWNTO 0); OMan : OUT std_logic_vector (25 DOWNTO 0); OExp : OUT std_logic_vector ( 8 DOWNTO 0); RunO : OUT std_logic); END Norm1; ARCHITECTURE RTL OF Norm1 IS SIGNAL ExpCorrect : std_logic_vector(7 DOWNTO 0); SIGNAL ShiftDistance : std_logic_vector(4 DOWNTO 0); BEGIN PROCESS (CLK,reset) --variable exp: std_logic_vector(7 downto 0); --variable manA,manB: std_logic_vector(24 downto 0); BEGIN IF (clk = '1' and clk'event) THEN IF (reset = '1') THEN ExpCorrect <= (OTHERS => '0'); ShiftDistance <= (OTHERS => '0'); OMan <= (OTHERS => '0'); OExp <= (OTHERS => '0'); ELSE RunO <= Run; IF (Run = '1') THEN --exp := UExp(7 downto 0); OMan <= UMan; IF (UMan(25) = '1') THEN -- Overflow from Hidden Bits ExpCorrect <= "00000001"; ShiftDistance <= "00000"; OExp <= UExp; ELSIF (UMan(24) = '1') THEN -- No need to adjust exponents ExpCorrect <= "00000000"; ShiftDistance <= "00001"; OExp <= UExp; ELSIF (UMan(23) = '1') THEN -- We need to adjust down ExpCorrect <= "11111111"; ShiftDistance <= "00010"; OExp <= UExp; ELSIF (UMan(22) = '1') THEN -- We need to adjust down ExpCorrect <= "11111110"; ShiftDistance <= "00011"; OExp <= UExp; ELSIF (UMan(21) = '1') THEN -- We need to adjust down ExpCorrect <= "11111101"; ShiftDistance <= "00100"; OExp <= UExp; ELSIF (UMan(20) = '1') THEN -- We need to adjust down ExpCorrect <= "11111100"; ShiftDistance <= "00101"; OExp <= UExp; ELSIF (UMan(19) = '1') THEN -- We need to adjust down ExpCorrect <= "11111011"; ShiftDistance <= "00110"; OExp <= UExp; ELSIF (UMan(18) = '1') THEN -- We need to adjust down ExpCorrect <= "11111010"; ShiftDistance <= "00111"; OExp <= UExp; ELSIF (UMan(17) = '1') THEN -- We need to adjust down ExpCorrect <= "11111001"; ShiftDistance <= "01000"; OExp <= UExp; ELSIF (UMan(16) = '1') THEN -- We need to adjust down ExpCorrect <= "11111000"; ShiftDistance <= "01001"; OExp <= UExp; ELSIF (UMan(15) = '1') THEN -- We need to adjust down ExpCorrect <= "11110111"; ShiftDistance <= "01010"; OExp <= UExp; ELSIF (UMan(14) = '1') THEN -- We need to adjust down ExpCorrect <= "11110110"; ShiftDistance <= "01011"; OExp <= UExp; ELSIF (UMan(13) = '1') THEN -- We need to adjust down ExpCorrect <= "11110101"; ShiftDistance <= "01100"; OExp <= UExp; ELSIF (UMan(12) = '1') THEN -- We need to adjust down ExpCorrect <= "11110100"; ShiftDistance <= "01101"; OExp <= UExp; ELSIF (UMan(11) = '1') THEN -- We need to adjust down ExpCorrect <= "11110011"; ShiftDistance <= "01110"; OExp <= UExp; ELSIF (UMan(10) = '1') THEN -- We need to adjust down ExpCorrect <= "11110010"; ShiftDistance <= "01111"; OExp <= UExp; ELSIF (UMan(9) = '1') THEN -- We need to adjust down ExpCorrect <= "11110001"; ShiftDistance <= "10000"; OExp <= UExp; ELSIF (UMan(8) = '1') THEN -- We need to adjust down ExpCorrect <= "11110000"; ShiftDistance <= "10001"; OExp <= UExp; ELSIF (UMan(7) = '1') THEN -- We need to adjust down ExpCorrect <= "11101111"; ShiftDistance <= "10010"; OExp <= UExp; ELSIF (UMan(6) = '1') THEN -- We need to adjust down ExpCorrect <= "11101110"; ShiftDistance <= "10011"; OExp <= UExp; ELSIF (UMan(5) = '1') THEN -- We need to adjust down ExpCorrect <= "11101101"; ShiftDistance <= "10100"; OExp <= UExp; ELSIF (UMan(4) = '1') THEN -- We need to adjust down ExpCorrect <= "11101100"; ShiftDistance <= "10101"; OExp <= UExp; ELSIF (UMan(3) = '1') THEN -- We need to adjust down ExpCorrect <= "11101011"; ShiftDistance <= "10110"; OExp <= UExp; ELSIF (UMan(2) = '1') THEN -- We need to adjust down ExpCorrect <= "11101010"; ShiftDistance <= "10111"; OExp <= UExp; ELSIF (UMan(1) = '1') THEN -- We need to adjust down ExpCorrect <= "11101010"; ShiftDistance <= "11000"; OExp <= UExp; ELSE -- Mantissa equals zero ExpCorrect <= "00000000"; ShiftDistance <= "00000"; OExp <="000000000"; END IF; END IF; -- END Run = '1' END IF; -- END IF reset = 0 END IF; -- END IF clk = '1' and clk'event END PROCESS; ExpCor <= ExpCorrect; ShfDst <= ShiftDistance; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: Floating Point Adder -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: June 1999 -- Description: -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned."+"; use IEEE.std_logic_unsigned."-"; use IEEE.std_logic_unsigned.">"; use IEEE.std_logic_unsigned.SHL; use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR; ENTITY Norm2 IS PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; ExpCor : IN std_logic_vector (7 DOWNTO 0); ShfDst : IN std_logic_vector (4 DOWNTO 0); UExp : IN std_logic_vector(8 DOWNTO 0); UMan : IN std_logic_vector(25 DOWNTO 0); Q : OUT std_logic_vector(31 DOWNTO 0); RunO : OUT std_logic); END Norm2; ARCHITECTURE RTL OF Norm2 IS SIGNAL QQ : std_logic_vector(31 DOWNTO 0); BEGIN PROCESS (CLK,reset) variable exp: std_logic_vector(7 downto 0); variable ManOut, ManA: std_logic_vector(25 downto 0); variable RoundMan : std_logic_vector(24 downto 0); --variable manA,manB: std_logic_vector(24 downto 0); BEGIN IF (clk = '1' and clk'event) THEN IF (reset = '1') THEN QQ <= (Others=> '0'); ELSE RunO <= Run; IF (Run = '1') THEN exp := UExp(7 DOWNTO 0); ManA := Uman; QQ(31) <= UExp(8); QQ(30 DOWNTO 23) <= exp + ExpCor; ManOut := SHL(ManA,ShfDst); RoundMan := ManOut(24 downto 0); IF ((RoundMan(1) = '1') AND (RoundMan(2) = '1') ) then -- Round the Mantissa RoundMan := RoundMan + "0000000000000000000000010"; END IF; QQ(22 downto 0) <= RoundMan(24 downto 2); END IF; -- END IF Run = '1' END IF; -- END IF reset = 0 END IF; -- END IF clk = '1' and clk'event END PROCESS; Q <= QQ; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: Six Stage Floating Point Adder Core -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: November 1999 -- Description: -- Pipelined. -------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_Logic_1164.all; ENTITY RegStage8 IS PORT(Ck : IN std_logic; Reset : IN std_logic; Run : IN std_logic; Datain : IN std_logic_vector(31 DOWNTO 0); Q : OUT std_logic_vector(31 DOWNTO 0); RunO : OUT std_logic); END RegStage8; ARCHITECTURE RTL OF RegStage8 IS SIGNAL D : std_logic_vector(31 DOWNTO 0); SIGNAL R : std_logic; BEGIN PROCESS BEGIN WAIT UNTIL ((Ck'EVENT) AND (Ck= '1')); IF (Reset = '1') THEN -- Changed Reset to Active High D <= "00000000000000000000000000000000"; R <= '0'; ELSIF (Run = '1') THEN D <= Datain; R <= Run; ELSE D <= D; R <= Run; END IF; END process; Q <= D; RunO <= R; END RTL; -------------------------------------------------------------- -- Copyright 2001 by Howard University All rights reserved. -- -- Design Name : 8 stage pipelined Floating Point Adder -- Name : Ibrahim Sahin & Clay Gloster -- Date : March 2001 -- Description : ------------------------------------------------------------- -------------------------------------------------------------- -- Copyright 2001 by Howard University All rights reserved. -- -- Design Name : 8 stage pipelined Floating Point Adder -- Name : Ibrahim Sahin & Clay Gloster -- Date : March 2001 -- Description : ------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; ENTITY FpAdderCore_8 IS PORT(clk : IN std_logic; reset : IN std_logic; EnR : IN std_logic; EnL : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); Op_Q : OUT std_logic_vector(31 DOWNTO 0); EnN : OUT std_logic); END FpAdderCore_8; ARCHITECTURE STRUCTURAL OF FpAdderCore_8 IS COMPONENT CompareExp PORT(clk : IN std_logic; reset : IN std_logic; EnR : IN std_logic; EnL : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); LExp : OUT std_logic_vector(7 DOWNTO 0); SExp : OUT std_logic_vector(7 DOWNTO 0); LMan : OUT std_logic_vector(22 DOWNTO 0); SMan : OUT std_logic_vector(22 DOWNTO 0); LSign : OUT std_logic; SSign : OUT std_logic; RunO : OUT std_logic); END COMPONENT; COMPONENT ComputeShift PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; LExp : IN std_logic_vector(7 DOWNTO 0); SExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(22 DOWNTO 0); SMan : IN std_logic_vector(22 DOWNTO 0); LSign : IN std_logic; SSign : IN std_logic; LExpP : OUT std_logic_vector(7 DOWNTO 0); SExpP : OUT std_logic_vector(7 DOWNTO 0); LManP : OUT std_logic_vector(22 DOWNTO 0); SManP : OUT std_logic_vector(22 DOWNTO 0); LSignP : OUT std_logic; SSignP : OUT std_logic; shiftdistance : OUT std_logic_vector(4 DOWNTO 0); RunO : OUT std_logic); END COMPONENT; COMPONENT ShiftMan PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; shiftdistance : IN std_logic_vector(4 DOWNTO 0); LExp : IN std_logic_vector(7 DOWNTO 0); SExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(22 DOWNTO 0); SMan : IN std_logic_vector(22 DOWNTO 0); LSign : IN std_logic; SSign : IN std_logic; LExpP : OUT std_logic_vector(7 DOWNTO 0); LManP : OUT std_logic_vector(24 DOWNTO 0); SManP : OUT std_logic_vector(24 DOWNTO 0); LSignP : OUT std_logic; SSignP : OUT std_logic; RunO : OUT std_logic); END COMPONENT; COMPONENT CompareMan PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; LSign : IN std_logic; LExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(24 DOWNTO 0); SSign : IN std_logic; SMan : IN std_logic_vector(24 DOWNTO 0); Exp : OUT std_logic_vector(7 DOWNTO 0); LMan1 : OUT std_logic_vector(24 DOWNTO 0); SMan1 : OUT std_logic_vector(24 DOWNTO 0); Sign : OUT std_logic; AddSub : OUT std_logic; RunO : OUT std_logic); END COMPONENT; COMPONENT AddSubMan PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; Sign : IN std_logic; AddSub : IN std_logic; Exp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(24 DOWNTO 0); SMan : IN std_logic_vector(24 DOWNTO 0); UExp : OUT std_logic_vector(8 DOWNTO 0); UMan : OUT std_logic_vector(25 DOWNTO 0); RunO : OUT std_logic); END COMPONENT; COMPONENT Norm1 PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; UMan : IN std_logic_vector(25 downto 0); UExp : IN std_logic_vector (8 DOWNTO 0); ExpCor : OUT std_logic_vector (7 DOWNTO 0); ShfDst : OUT std_logic_vector (4 DOWNTO 0); OMan : OUT std_logic_vector (25 DOWNTO 0); OExp : OUT std_logic_vector (8 DOWNTO 0); RunO : OUT std_logic); END COMPONENT; COMPONENT Norm2 PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; ExpCor : IN std_logic_vector (7 DOWNTO 0); ShfDst : IN std_logic_vector (4 DOWNTO 0); UExp : IN std_logic_vector (8 DOWNTO 0); UMan : IN std_logic_vector (25 DOWNTO 0); Q : OUT std_logic_vector(31 DOWNTO 0); RunO : OUT std_logic); END COMPONENT; COMPONENT RegStage8 PORT(Ck : IN std_logic; Reset : IN std_logic; Run : IN std_logic; Datain : IN std_logic_vector(31 DOWNTO 0); Q : OUT std_logic_vector(31 DOWNTO 0); RunO : OUT std_logic); END COMPONENT; SIGNAL LExp12 : std_logic_vector(7 downto 0); SIGNAL SExp12 : std_logic_vector(7 downto 0); SIGNAL LMan12 : std_logic_vector(22 downto 0); SIGNAL SMan12 : std_logic_vector(22 downto 0); SIGNAL LSign12 : std_logic; SIGNAL SSign12 : std_logic; SIGNAL RunO12 : std_logic; SIGNAL LExpP23 : std_logic_vector(7 downto 0); SIGNAL SExpP23 : std_logic_vector(7 downto 0); SIGNAL LManP23 : std_logic_vector(22 downto 0); SIGNAL SManP23 : std_logic_vector(22 downto 0); SIGNAL LSignP23 : std_logic; SIGNAL SSignP23 : std_logic; SIGNAL shiftdistance23 : std_logic_vector(4 downto 0); SIGNAL RunO23 : std_logic; SIGNAL LExpP34 : std_logic_vector(7 DOWNTO 0); SIGNAL LManP34 : std_logic_vector(24 DOWNTO 0); SIGNAL SManP34 : std_logic_vector(24 DOWNTO 0); SIGNAL LSignP34 : std_logic; SIGNAL SSignP34 : std_logic; SIGNAL RunO34 : std_logic; SIGNAL Exp45 : std_logic_vector(7 DOWNTO 0); SIGNAL LMan145 : std_logic_vector(24 DOWNTO 0); SIGNAL SMan145 : std_logic_vector(24 DOWNTO 0); SIGNAL Sign45 : std_logic; SIGNAL AddSub45 : std_logic; SIGNAL RunO45 : std_logic; SIGNAL UExp56 : std_logic_vector(8 DOWNTO 0); SIGNAL UMan56 : std_logic_vector(25 DOWNTO 0); SIGNAL RunO56 : std_logic; SIGNAL ExpCor67 : std_logic_vector (7 DOWNTO 0); SIGNAL ShfDst67 : std_logic_vector (4 DOWNTO 0); SIGNAL OExp67 : std_logic_vector(8 DOWNTO 0); SIGNAL OMan67 : std_logic_vector(25 DOWNTO 0); SIGNAL RunO67 : std_logic; SIGNAL Q78 : std_logic_vector(31 DOWNTO 0); SIGNAL RunO78 : std_logic; BEGIN Inst1: CompareExp PORT MAP (clk, reset, EnR, EnL, Op_A, Op_B, LExp12, SExp12, LMan12, SMan12, LSign12, SSign12, RunO12); Inst2: ComputeShift PORT MAP (clk, reset, RunO12, LExp12, SExp12, LMan12, SMan12, LSign12, SSign12, LExpP23, SExpP23, LManP23, SManP23, LSignP23, SSignP23, shiftdistance23, RunO23); Inst3: ShiftMan PORT MAP (clk, reset, RunO23, shiftdistance23, LExpP23, SExpP23, LManP23, SManP23, LSignP23, SSignP23, LExpP34, LManP34, SManP34, LSignP34, SSignP34, RunO34); Inst4: CompareMan PORT MAP (clk, reset, RunO34, LSignP34, LExpP34, LManP34, SSignP34, SManP34, Exp45, LMan145, SMan145, Sign45, AddSub45, RunO45); Inst5: AddSubMan PORT MAP (clk ,reset, RunO45, Sign45, AddSub45, Exp45, LMan145, SMan145, UExp56, UMan56, RunO56); Inst6: Norm1 PORT MAP (clk, reset, RunO56, UMan56, UExp56, ExpCor67, ShfDst67, OMan67, OExp67, RunO67); Inst7: Norm2 PORT MAP (clk, reset, RunO67, ExpCor67, ShfDst67, OExp67, OMan67, Q78, RunO78); Inst8: RegStage8 PORT MAP (clk, reset, RunO78, Q78, Op_Q, EnN); END STRUCTURAL; -------------------------------------------------------------- -- Copyright 2001 by Howard University All rights reserved. -- -- Design Name : 8 stage pipelined Floating Point Subtractor -- Name : Ibrahim Sahin & Clay Gloster -- Date : March 2001 -- Description : ------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; ENTITY FpSubCore_8 IS PORT(clk : IN std_logic; reset : IN std_logic; EnR : IN std_logic; EnL : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); Op_Q : OUT std_logic_vector(31 DOWNTO 0); EnN : OUT std_logic); END FpSubCore_8; ARCHITECTURE STRUCTURAL OF FpSubCore_8 IS COMPONENT SubCompareExp PORT(clk : IN std_logic; reset : IN std_logic; EnR : IN std_logic; EnL : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); LExp : OUT std_logic_vector(7 DOWNTO 0); SExp : OUT std_logic_vector(7 DOWNTO 0); LMan : OUT std_logic_vector(22 DOWNTO 0); SMan : OUT std_logic_vector(22 DOWNTO 0); LSign : OUT std_logic; SSign : OUT std_logic; RunO : OUT std_logic); END COMPONENT; COMPONENT ComputeShift PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; LExp : IN std_logic_vector(7 DOWNTO 0); SExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(22 DOWNTO 0); SMan : IN std_logic_vector(22 DOWNTO 0); LSign : IN std_logic; SSign : IN std_logic; LExpP : OUT std_logic_vector(7 DOWNTO 0); SExpP : OUT std_logic_vector(7 DOWNTO 0); LManP : OUT std_logic_vector(22 DOWNTO 0); SManP : OUT std_logic_vector(22 DOWNTO 0); LSignP : OUT std_logic; SSignP : OUT std_logic; shiftdistance : OUT std_logic_vector(4 DOWNTO 0); RunO : OUT std_logic); END COMPONENT; COMPONENT ShiftMan PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; shiftdistance : IN std_logic_vector(4 DOWNTO 0); LExp : IN std_logic_vector(7 DOWNTO 0); SExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(22 DOWNTO 0); SMan : IN std_logic_vector(22 DOWNTO 0); LSign : IN std_logic; SSign : IN std_logic; LExpP : OUT std_logic_vector(7 DOWNTO 0); LManP : OUT std_logic_vector(24 DOWNTO 0); SManP : OUT std_logic_vector(24 DOWNTO 0); LSignP : OUT std_logic; SSignP : OUT std_logic; RunO : OUT std_logic); END COMPONENT; COMPONENT CompareMan PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; LSign : IN std_logic; LExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(24 DOWNTO 0); SSign : IN std_logic; SMan : IN std_logic_vector(24 DOWNTO 0); Exp : OUT std_logic_vector(7 DOWNTO 0); LMan1 : OUT std_logic_vector(24 DOWNTO 0); SMan1 : OUT std_logic_vector(24 DOWNTO 0); Sign : OUT std_logic; AddSub : OUT std_logic; RunO : OUT std_logic); END COMPONENT; COMPONENT AddSubMan PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; Sign : IN std_logic; AddSub : IN std_logic; Exp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(24 DOWNTO 0); SMan : IN std_logic_vector(24 DOWNTO 0); UExp : OUT std_logic_vector(8 DOWNTO 0); UMan : OUT std_logic_vector(25 DOWNTO 0); RunO : OUT std_logic); END COMPONENT; COMPONENT Norm1 PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; UMan : IN std_logic_vector(25 downto 0); UExp : IN std_logic_vector (8 DOWNTO 0); ExpCor : OUT std_logic_vector (7 DOWNTO 0); ShfDst : OUT std_logic_vector (4 DOWNTO 0); OMan : OUT std_logic_vector (25 DOWNTO 0); OExp : OUT std_logic_vector (8 DOWNTO 0); RunO : OUT std_logic); END COMPONENT; COMPONENT Norm2 PORT(clk : IN std_logic; reset : IN std_logic; Run : IN std_logic; ExpCor : IN std_logic_vector (7 DOWNTO 0); ShfDst : IN std_logic_vector (4 DOWNTO 0); UExp : IN std_logic_vector (8 DOWNTO 0); UMan : IN std_logic_vector (25 DOWNTO 0); Q : OUT std_logic_vector(31 DOWNTO 0); RunO : OUT std_logic); END COMPONENT; COMPONENT RegStage8 PORT(Ck : IN std_logic; Reset : IN std_logic; Run : IN std_logic; Datain : IN std_logic_vector(31 DOWNTO 0); Q : OUT std_logic_vector(31 DOWNTO 0); RunO : OUT std_logic); END COMPONENT; SIGNAL LExp12 : std_logic_vector(7 downto 0); SIGNAL SExp12 : std_logic_vector(7 downto 0); SIGNAL LMan12 : std_logic_vector(22 downto 0); SIGNAL SMan12 : std_logic_vector(22 downto 0); SIGNAL LSign12 : std_logic; SIGNAL SSign12 : std_logic; SIGNAL RunO12 : std_logic; SIGNAL LExpP23 : std_logic_vector(7 downto 0); SIGNAL SExpP23 : std_logic_vector(7 downto 0); SIGNAL LManP23 : std_logic_vector(22 downto 0); SIGNAL SManP23 : std_logic_vector(22 downto 0); SIGNAL LSignP23 : std_logic; SIGNAL SSignP23 : std_logic; SIGNAL shiftdistance23 : std_logic_vector(4 downto 0); SIGNAL RunO23 : std_logic; SIGNAL LExpP34 : std_logic_vector(7 DOWNTO 0); SIGNAL LManP34 : std_logic_vector(24 DOWNTO 0); SIGNAL SManP34 : std_logic_vector(24 DOWNTO 0); SIGNAL LSignP34 : std_logic; SIGNAL SSignP34 : std_logic; SIGNAL RunO34 : std_logic; SIGNAL Exp45 : std_logic_vector(7 DOWNTO 0); SIGNAL LMan45 : std_logic_vector(24 DOWNTO 0); SIGNAL SMan45 : std_logic_vector(24 DOWNTO 0); SIGNAL Sign45 : std_logic; SIGNAL AddSub45 : std_logic; SIGNAL RunO45 : std_logic; SIGNAL UExp56 : std_logic_vector(8 DOWNTO 0); SIGNAL UMan56 : std_logic_vector(25 DOWNTO 0); SIGNAL RunO56 : std_logic; SIGNAL ExpCor67 : std_logic_vector (7 DOWNTO 0); SIGNAL ShfDst67 : std_logic_vector (4 DOWNTO 0); SIGNAL OExp67 : std_logic_vector(8 DOWNTO 0); SIGNAL OMan67 : std_logic_vector(25 DOWNTO 0); SIGNAL RunO67 : std_logic; SIGNAL Q78 : std_logic_vector(31 DOWNTO 0); SIGNAL RunO78 : std_logic; BEGIN Inst1: SubCompareExp PORT MAP (clk, reset, EnR, EnL, Op_A, Op_B, LExp12, SExp12, LMan12, SMan12, LSign12, SSign12, RunO12); Inst2: ComputeShift PORT MAP (clk, reset, RunO12, LExp12, SExp12, LMan12, SMan12, LSign12, SSign12, LExpP23, SExpP23, LManP23, SManP23, LSignP23, SSignP23, shiftdistance23, RunO23); Inst3: ShiftMan PORT MAP (clk, reset, RunO23, shiftdistance23, LExpP23, SExpP23, LManP23, SManP23, LSignP23, SSignP23, LExpP34, LManP34, SManP34, LSignP34, SSignP34, RunO34); Inst4: CompareMan PORT MAP (clk, reset, RunO34, LSignP34, LExpP34, LManP34, SSignP34, SManP34, Exp45, LMan45, SMan45, Sign45, AddSub45, RunO45); Inst5: AddSubMan PORT MAP (clk ,reset, RunO45, Sign45, AddSub45, Exp45, LMan45, SMan45, UExp56, UMan56, RunO56); Inst6: Norm1 PORT MAP (clk, reset, RunO56, UMan56, UExp56, ExpCor67, ShfDst67, OMan67, OExp67, RunO67); Inst7: Norm2 PORT MAP (clk, reset, RunO67, ExpCor67, ShfDst67, OExp67, OMan67, Q78, RunO78); Inst8: RegStage8 PORT MAP (clk, reset, RunO78, Q78, Op_Q, EnN); END STRUCTURAL; -------------------------------------------------------------- -- Copyright 2001 by Howard University All rights reserved. -- -- Design Name : 8 stage pipelined Floating Point Adder and 8 stage -- Floating point Subtractor Core (See bottom of file) -- This Core holds the data in each stage until the enable is asserted. -- Name : Ibrahim Sahin & Clay Gloster -- Date : September 2001 -- Description : -------------------------------------------------------------- -----------------PARTS IN THE ADDER--------------------------- -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: SubCompareExp_comb -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: October 1999 -- Description: This is the first stage of the subtractor, it complements the -- Sign Bit. -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; ENTITY SubCompareExp_comb IS PORT( Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); LExp : OUT std_logic_vector(7 DOWNTO 0); SExp : OUT std_logic_vector(7 DOWNTO 0); LMan : OUT std_logic_vector(22 DOWNTO 0); SMan : OUT std_logic_vector(22 DOWNTO 0); LSign : OUT std_logic; SSign : OUT std_logic); END SubCompareExp_comb; ARCHITECTURE RTL OF SubCompareExp_comb IS BEGIN PROCESS (Op_A,Op_B) variable expA,expB: std_logic_vector(8 DOWNTO 0); BEGIN expA := '0' & Op_A(30 DOWNTO 23); expB := '0' & Op_B(30 DOWNTO 23); IF (expA > expB) THEN IF (Op_B(30 DOWNTO 0) = "0000000000000000000000000000000") THEN SSign <= '0'; ELSE SSign <= not Op_B(31); END IF; SExp <= Op_B(30 DOWNTO 23); SMan <= Op_B(22 DOWNTO 0); LSign <= Op_A(31); LExp <= Op_A(30 DOWNTO 23); LMan <= Op_A(22 DOWNTO 0); ELSE SSign <= Op_A(31); SExp <= Op_A(30 DOWNTO 23); SMan <= Op_A(22 DOWNTO 0); IF (Op_B(30 DOWNTO 0) = "0000000000000000000000000000000") THEN LSign <= '0'; ELSE LSign <= not Op_B(31); END IF; LExp <= Op_B(30 DOWNTO 23); LMan <= Op_B(22 DOWNTO 0); END IF; END PROCESS; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: CompareExp_comb -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: October 1999 -- Description: This is the first stage of the adder core -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; ENTITY CompareExp_comb IS PORT( Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); LExp : OUT std_logic_vector(7 DOWNTO 0); SExp : OUT std_logic_vector(7 DOWNTO 0); LMan : OUT std_logic_vector(22 DOWNTO 0); SMan : OUT std_logic_vector(22 DOWNTO 0); LSign : OUT std_logic; SSign : OUT std_logic); END CompareExp_comb; ARCHITECTURE RTL OF CompareExp_comb IS BEGIN PROCESS (Op_A,Op_B) variable expA,expB: std_logic_vector(8 DOWNTO 0); BEGIN expA := '0' & Op_A(30 DOWNTO 23); expB := '0' & Op_B(30 DOWNTO 23); IF (expA > expB) THEN SSign <= Op_B(31); SExp <= Op_B(30 DOWNTO 23); SMan <= Op_B(22 DOWNTO 0); LSign <= Op_A(31); LExp <= Op_A(30 DOWNTO 23); LMan <= Op_A(22 DOWNTO 0); ELSE SSign <= Op_A(31); SExp <= Op_A(30 DOWNTO 23); SMan <= Op_A(22 DOWNTO 0); LSign <= Op_B(31); LExp <= Op_B(30 DOWNTO 23); LMan <= Op_B(22 DOWNTO 0); END IF; END PROCESS; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: ComputeShift_comb -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: October 1999 -- Description: -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned."-"; use IEEE.std_logic_unsigned.">"; use IEEE.std_logic_unsigned.SHR; use IEEE.std_logic_unsigned.CONV_INTEGER; use IEEE.std_logic_misc.OR_REDUCE; use IEEE.std_logic_arith.all; ENTITY ComputeShift_comb IS PORT( LExp : IN std_logic_vector(7 DOWNTO 0); SExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(22 DOWNTO 0); SMan : IN std_logic_vector(22 DOWNTO 0); LSign : IN std_logic; SSign : IN std_logic; LExpP : OUT std_logic_vector(7 DOWNTO 0); SExpP : OUT std_logic_vector(7 DOWNTO 0); LManP : OUT std_logic_vector(22 DOWNTO 0); SManP : OUT std_logic_vector(22 DOWNTO 0); LSignP : OUT std_logic; SSignP : OUT std_logic; shiftdistance : OUT std_logic_vector(4 DOWNTO 0)); END ComputeShift_comb; ARCHITECTURE RTL OF ComputeShift_comb IS BEGIN PROCESS (LExp,SExp,LMan,SMan,LSign,SSign) variable sdistance: std_logic_vector(7 DOWNTO 0); BEGIN sdistance := LExp - SExp; LExpP <= LExp; SExpP<= SExp; LManP <= LMan; SManP<=SMan; LSignP <= LSign; SSignP <= SSign; shiftdistance <= sdistance(4 DOWNTO 0); END PROCESS; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: ShiftMan_comb -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: October 1999 -- Description: -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.">"; use IEEE.std_logic_unsigned.SHR; use IEEE.std_logic_unsigned.CONV_INTEGER; use IEEE.std_logic_misc.OR_REDUCE; use IEEE.std_logic_arith.all; ENTITY ShiftMan_comb IS PORT( shiftdistance : IN std_logic_vector(4 DOWNTO 0); LExp : IN std_logic_vector(7 DOWNTO 0); SExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(22 DOWNTO 0); SMan : IN std_logic_vector(22 DOWNTO 0); LSign : IN std_logic; SSign : IN std_logic; LExpP : OUT std_logic_vector(7 DOWNTO 0); LManP : OUT std_logic_vector(23 DOWNTO 0); SManP : OUT std_logic_vector(23 DOWNTO 0); LSignP : OUT std_logic; SSignP : OUT std_logic); END ShiftMan_comb; ARCHITECTURE RTL OF ShiftMan_comb IS BEGIN PROCESS (shiftdistance,LExp,SExp,LMan,SMan,LSign,SSign) variable manA,manB: std_logic_vector(23 DOWNTO 0); variable bitA,bitB: std_logic; BEGIN -- Add Hidden Bits to Manitissas bitA := LSign OR OR_REDUCE(LMan) OR OR_REDUCE(LExp); manA := bitA&LMan(22 downto 0); bitB := SSign OR OR_REDUCE(SMan) OR OR_REDUCE(SExp); manB := bitB&SMan(22 downto 0); SManP <= SHR(manB,shiftdistance); LExpP <= LExp; LManP <= manA; LSignP <= LSign; SSignP <= SSign; END PROCESS; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: CompareMan_comb -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: November 1999 -- Description: -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned."+"; use IEEE.std_logic_unsigned."-"; use IEEE.std_logic_unsigned.SHL; use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR; ENTITY CompareMan_comb IS PORT( LSign : IN std_logic; LExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(23 DOWNTO 0); SSign : IN std_logic; SMan : IN std_logic_vector(23 DOWNTO 0); Exp : OUT std_logic_vector(7 DOWNTO 0); LMan1 : OUT std_logic_vector(23 DOWNTO 0); SMan1 : OUT std_logic_vector(23 DOWNTO 0); Sign : OUT std_logic; AddSub : OUT std_logic); END CompareMan_comb; ARCHITECTURE RTL OF CompareMan_comb IS BEGIN PROCESS (LSign,LExp,LMan,SSign,SMan) BEGIN IF (LSign = SSign) THEN -- Signs of the two numbers are the same Sign <= LSign; LMan1 <= LMan; SMan1 <= SMan; AddSub <= '0'; ELSE -- Signs are different IF (LMan > SMan) THEN Sign <= LSign; AddSub <= '1'; LMan1 <= LMan; SMan1 <= SMan; ELSE Sign <= SSign; AddSub <= '1'; LMan1 <= SMan; SMan1 <= LMan; END IF; END IF; -- END IF LSIgn = SSign Exp <= LExp; END PROCESS; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: AddSubMan_comb -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: June 1999 -- Description: -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned."+"; use IEEE.std_logic_unsigned."-"; use IEEE.std_logic_unsigned.">"; use IEEE.std_logic_unsigned.SHL; use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR; ENTITY AddSubMan_comb IS PORT( Sign : IN std_logic; AddSub : IN std_logic; Exp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(23 DOWNTO 0); SMan : IN std_logic_vector(23 DOWNTO 0); UExp : OUT std_logic_vector(8 DOWNTO 0); UMan : OUT std_logic_vector(24 DOWNTO 0)); END AddSubMan_comb; ARCHITECTURE RTL OF AddSubMan_comb IS BEGIN PROCESS (Sign,AddSub,Exp,LMan,SMan) variable NewMan: std_logic_vector(24 DOWNTO 0); variable manA,manB: std_logic_vector(24 DOWNTO 0); BEGIN manA := '0' & LMan; manB := '0' & SMan; IF (AddSub = '0') THEN -- We need to add the mantissas NewMan := manA + manB; ELSE -- We need to subtract the mantissas NewMan:=manA - manB; END IF; -- END IF LSIgn = SSign UExp(7 downto 0) <= Exp; UMan <= NewMan; UExp(8) <= Sign; END PROCESS; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: Floating Point Adder -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: June 1999 -- Description: -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned."+"; use IEEE.std_logic_unsigned."-"; use IEEE.std_logic_unsigned.">"; use IEEE.std_logic_unsigned.SHL; use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR; ENTITY Norm1_comb IS PORT( UMan : IN std_logic_vector (24 DOWNTO 0); UExp : IN std_logic_vector ( 8 DOWNTO 0); ExpCor : OUT std_logic_vector ( 7 DOWNTO 0); ShfDst : OUT std_logic_vector ( 4 DOWNTO 0); OMan : OUT std_logic_vector (24 DOWNTO 0); OExp : OUT std_logic_vector ( 8 DOWNTO 0)); END Norm1_comb; ARCHITECTURE RTL OF Norm1_comb IS SIGNAL ExpCorrect : std_logic_vector(7 DOWNTO 0); SIGNAL ShiftDistance : std_logic_vector(4 DOWNTO 0); BEGIN PROCESS (UMan,UExp) --variable exp: std_logic_vector(7 downto 0); --variable manA,manB: std_logic_vector(24 downto 0); BEGIN --exp := UExp(7 downto 0); OMan <= UMan; IF (UMan(24) = '1') THEN -- Overflow from Hidden Bits ExpCorrect <= "00000001"; ShiftDistance <= "00000"; OExp <= UExp; ELSIF (UMan(23) = '1') THEN -- No need to adjust exponents ExpCorrect <= "00000000"; ShiftDistance <= "00001"; OExp <= UExp; ELSIF (UMan(22) = '1') THEN -- We need to adjust down ExpCorrect <= "11111111"; ShiftDistance <= "00010"; OExp <= UExp; ELSIF (UMan(21) = '1') THEN -- We need to adjust down ExpCorrect <= "11111110"; ShiftDistance <= "00011"; OExp <= UExp; ELSIF (UMan(20) = '1') THEN -- We need to adjust down ExpCorrect <= "11111101"; ShiftDistance <= "00100"; OExp <= UExp; ELSIF (UMan(19) = '1') THEN -- We need to adjust down ExpCorrect <= "11111100"; ShiftDistance <= "00101"; OExp <= UExp; ELSIF (UMan(18) = '1') THEN -- We need to adjust down ExpCorrect <= "11111011"; ShiftDistance <= "00110"; OExp <= UExp; ELSIF (UMan(17) = '1') THEN -- We need to adjust down ExpCorrect <= "11111010"; ShiftDistance <= "00111"; OExp <= UExp; ELSIF (UMan(16) = '1') THEN -- We need to adjust down ExpCorrect <= "11111001"; ShiftDistance <= "01000"; OExp <= UExp; ELSIF (UMan(15) = '1') THEN -- We need to adjust down ExpCorrect <= "11111000"; ShiftDistance <= "01001"; OExp <= UExp; ELSIF (UMan(14) = '1') THEN -- We need to adjust down ExpCorrect <= "11110111"; ShiftDistance <= "01010"; OExp <= UExp; ELSIF (UMan(13) = '1') THEN -- We need to adjust down ExpCorrect <= "11110110"; ShiftDistance <= "01011"; OExp <= UExp; ELSIF (UMan(12) = '1') THEN -- We need to adjust down ExpCorrect <= "11110101"; ShiftDistance <= "01100"; OExp <= UExp; ELSIF (UMan(11) = '1') THEN -- We need to adjust down ExpCorrect <= "11110100"; ShiftDistance <= "01101"; OExp <= UExp; ELSIF (UMan(10) = '1') THEN -- We need to adjust down ExpCorrect <= "11110011"; ShiftDistance <= "01110"; OExp <= UExp; ELSIF (UMan(9) = '1') THEN -- We need to adjust down ExpCorrect <= "11110010"; ShiftDistance <= "01111"; OExp <= UExp; ELSIF (UMan(8) = '1') THEN -- We need to adjust down ExpCorrect <= "11110001"; ShiftDistance <= "10000"; OExp <= UExp; ELSIF (UMan(7) = '1') THEN -- We need to adjust down ExpCorrect <= "11110000"; ShiftDistance <= "10001"; OExp <= UExp; ELSIF (UMan(6) = '1') THEN -- We need to adjust down ExpCorrect <= "11101111"; ShiftDistance <= "10010"; OExp <= UExp; ELSIF (UMan(5) = '1') THEN -- We need to adjust down ExpCorrect <= "11101110"; ShiftDistance <= "10011"; OExp <= UExp; ELSIF (UMan(4) = '1') THEN -- We need to adjust down ExpCorrect <= "11101101"; ShiftDistance <= "10100"; OExp <= UExp; ELSIF (UMan(3) = '1') THEN -- We need to adjust down ExpCorrect <= "11101100"; ShiftDistance <= "10101"; OExp <= UExp; ELSIF (UMan(2) = '1') THEN -- We need to adjust down ExpCorrect <= "11101011"; ShiftDistance <= "10110"; OExp <= UExp; ELSIF (UMan(1) = '1') THEN -- We need to adjust down ExpCorrect <= "11101010"; ShiftDistance <= "10111"; OExp <= UExp; ELSIF (UMan(0) = '1') THEN -- We need to adjust down ExpCorrect <= "11101010"; ShiftDistance <= "11000"; OExp <= UExp; ELSE -- Mantissa equals zero ExpCorrect <= "00000000"; ShiftDistance <= "00000"; OExp <="000000000"; END IF; END PROCESS; ExpCor <= ExpCorrect; ShfDst <= ShiftDistance; END RTL; -------------------------------------------------------------- -- Copyright 1999 by Howard University All rights reserved. -- -- Design: Floating Point Adder -- Name: Clay Gloster & Ibrahim Sahin -- -- Date: June 1999 -- Description: -- Pipelined. -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned."+"; use IEEE.std_logic_unsigned."-"; use IEEE.std_logic_unsigned.">"; use IEEE.std_logic_unsigned.SHL; use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR; ENTITY Norm2_comb IS PORT( ExpCor : IN std_logic_vector (7 DOWNTO 0); ShfDst : IN std_logic_vector (4 DOWNTO 0); UExp : IN std_logic_vector(8 DOWNTO 0); UMan : IN std_logic_vector(24 DOWNTO 0); Q : OUT std_logic_vector(31 DOWNTO 0)); END Norm2_comb; ARCHITECTURE RTL OF Norm2_comb IS SIGNAL QQ : std_logic_vector(31 DOWNTO 0); BEGIN PROCESS (ExpCor,ShfDst,UExp,UMan) variable exp: std_logic_vector(7 downto 0); variable ManOut, ManA: std_logic_vector(23 downto 0); variable RoundMan : std_logic_vector(22 downto 0); --variable manA,manB: std_logic_vector(24 downto 0); BEGIN exp := UExp(7 DOWNTO 0); ManA := Uman (23 DOWNTO 0); QQ(31) <= UExp(8); QQ(30 DOWNTO 23) <= exp + ExpCor; ManOut := SHL(ManA,ShfDst); RoundMan := ManOut(23 downto 1); IF (ManOut(1) = '1' AND ManOut(0) = '1' ) then -- Round the Mantissa RoundMan := RoundMan + "00000000000000000000001"; END IF; QQ(22 downto 0) <= RoundMan; END PROCESS; Q <= QQ; END RTL; --------------------------------------------------------------- --Copyright 2001 by Howard University All rights reserved. -- --Design: Generic Register --Name: Clay Gloster -- --Date: May 2001 --Description: Generic Register --Width equal to one --Does not have parallel --------------------------------------------------------------- library IEEE; use IEEE.STD_Logic_1164.all; entity REG_GENERIC_ENABLE is generic (Width : integer); port (Datain : in std_logic_vector(Width-1 downto 0); Clk,Reset,Enable : in std_logic; Q: out std_logic_vector(Width-1 downto 0) ); end REG_GENERIC_ENABLE; architecture RTL of REG_GENERIC_ENABLE is signal D: std_logic_vector(Width-1 downto 0); begin start: process(Clk) variable i: integer; begin if (Clk'EVENT and Clk = '1') then if (Reset = '1') then -- Changed Reset to Active High for i in 0 to Width-1 loop D(i) <= '0'; end loop; elsif (Enable = '1') then D <= Datain; else D <= D; end if; -- End if Reset = '1' end if; -- End if Clk'Event and Clk = '1' end process; Q <= D; end RTL; --------------------------------------------------------------- --Copyright 2001 by Howard University All rights reserved. -- --Design: DFF 1bit with Enable --Name: Clay Gloster -- --Date: May 2001 --Description: Generic Register --Width equal to one --Does not have parallel --------------------------------------------------------------- library IEEE; use IEEE.STD_Logic_1164.all; entity REG_1bit_ENABLE is port (Datain : in std_logic; Clk,Reset,Enable : in std_logic; Q: out std_logic); end REG_1bit_ENABLE; architecture RTL of REG_1bit_ENABLE is signal D: std_logic; begin start: process(Clk) variable i: integer; begin if (Clk'EVENT and Clk = '1') then if (Reset = '1') then -- Changed Reset to Active High D <= '0'; elsif (Enable = '1') then D <= Datain; else D <= D; end if; -- End if Reset = '1' end if; -- End if Clk'Event and Clk = '1' end process; Q <= D; end RTL; --------------------------------------------------------------- --Copyright 2001 by Howard University All rights reserved. -- --Design: Shift Register --Name: Clay Gloster -- --Date: October 2001 --Description: -- -- --------------------------------------------------------------- library IEEE; use IEEE.STD_Logic_1164.all; entity shiftregister is generic (Width : integer); port (Datain : in std_logic; Clk,Reset,Enable : in std_logic; Q: out std_logic); end shiftregister; architecture structural of shiftregister is component REG_1bit_ENABLE port (Datain : in std_logic; Clk,Reset,Enable: in std_logic; Q: out std_logic); end component; signal REGIO : std_logic_vector(0 to Width); begin lpp1: for i in 0 to Width-1 generate I0: REG_1bit_ENABLE port map ( REGIO(i), Clk, Reset, Enable, REGIO(i+1) ); end generate; REGIO(0) <= Datain; Q <= REGIO(Width); end structural; --------------------------------------------------------------- -------------------------------------------------------------- -- Copyright 2001 by Howard University All rights reserved. -- -- Design Name : 8 stage pipelined Floating Point Adder -- Name : Ibrahim Sahin & Clay Gloster -- Date : March 2001 -- Description : ------------------------------------------------------------- -------------------------------------------------------------- -- Copyright 2001 by Howard University All rights reserved. -- -- Design Name : 8 stage pipelined Floating Point Adder -- Name : Ibrahim Sahin & Clay Gloster -- Date : March 2001 -- Description : ------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; ENTITY FpAdderCore_8_hold IS PORT(clk : IN std_logic; reset : IN std_logic; Enable : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); Op_Q : OUT std_logic_vector(31 DOWNTO 0); Done : OUT std_logic); END FpAdderCore_8_hold; ARCHITECTURE STRUCTURAL OF FpAdderCore_8_hold IS COMPONENT CompareExp_comb PORT( Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); LExp : OUT std_logic_vector(7 DOWNTO 0); SExp : OUT std_logic_vector(7 DOWNTO 0); LMan : OUT std_logic_vector(22 DOWNTO 0); SMan : OUT std_logic_vector(22 DOWNTO 0); LSign : OUT std_logic; SSign : OUT std_logic); END COMPONENT; COMPONENT ComputeShift_comb PORT( LExp : IN std_logic_vector(7 DOWNTO 0); SExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(22 DOWNTO 0); SMan : IN std_logic_vector(22 DOWNTO 0); LSign : IN std_logic; SSign : IN std_logic; LExpP : OUT std_logic_vector(7 DOWNTO 0); SExpP : OUT std_logic_vector(7 DOWNTO 0); LManP : OUT std_logic_vector(22 DOWNTO 0); SManP : OUT std_logic_vector(22 DOWNTO 0); LSignP : OUT std_logic; SSignP : OUT std_logic; shiftdistance : OUT std_logic_vector(4 DOWNTO 0)); END COMPONENT; COMPONENT ShiftMan_comb PORT( shiftdistance : IN std_logic_vector(4 DOWNTO 0); LExp : IN std_logic_vector(7 DOWNTO 0); SExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(22 DOWNTO 0); SMan : IN std_logic_vector(22 DOWNTO 0); LSign : IN std_logic; SSign : IN std_logic; LExpP : OUT std_logic_vector(7 DOWNTO 0); LManP : OUT std_logic_vector(23 DOWNTO 0); SManP : OUT std_logic_vector(23 DOWNTO 0); LSignP : OUT std_logic; SSignP : OUT std_logic); END COMPONENT; COMPONENT CompareMan_comb PORT( LSign : IN std_logic; LExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(23 DOWNTO 0); SSign : IN std_logic; SMan : IN std_logic_vector(23 DOWNTO 0); Exp : OUT std_logic_vector(7 DOWNTO 0); LMan1 : OUT std_logic_vector(23 DOWNTO 0); SMan1 : OUT std_logic_vector(23 DOWNTO 0); Sign : OUT std_logic; AddSub : OUT std_logic); END COMPONENT; COMPONENT AddSubMan_comb PORT( Sign : IN std_logic; AddSub : IN std_logic; Exp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(23 DOWNTO 0); SMan : IN std_logic_vector(23 DOWNTO 0); UExp : OUT std_logic_vector(8 DOWNTO 0); UMan : OUT std_logic_vector(24 DOWNTO 0)); END COMPONENT; COMPONENT Norm1_comb PORT( UMan : IN std_logic_vector(24 downto 0); UExp : IN std_logic_vector (8 DOWNTO 0); ExpCor : OUT std_logic_vector (7 DOWNTO 0); ShfDst : OUT std_logic_vector (4 DOWNTO 0); OMan : OUT std_logic_vector (24 DOWNTO 0); OExp : OUT std_logic_vector (8 DOWNTO 0)); END COMPONENT; COMPONENT Norm2_comb PORT( ExpCor : IN std_logic_vector (7 DOWNTO 0); ShfDst : IN std_logic_vector (4 DOWNTO 0); UExp : IN std_logic_vector (8 DOWNTO 0); UMan : IN std_logic_vector (24 DOWNTO 0); Q : OUT std_logic_vector(31 DOWNTO 0)); END COMPONENT; COMPONENT REG_GENERIC_ENABLE generic (Width : integer); port (Datain : in std_logic_vector(Width-1 downto 0); Clk,Reset,Enable : in std_logic; Q: out std_logic_vector(Width-1 downto 0) ); END COMPONENT; COMPONENT REG_1bit_ENABLE port (Datain : in std_logic; Clk,Reset,Enable : in std_logic; Q: out std_logic); end COMPONENT; COMPONENT shiftregister generic (Width : integer); port (Datain : in std_logic; Clk,Reset,Enable : in std_logic; Q: out std_logic); end COMPONENT; SIGNAL LExp12, LExp12_o : std_logic_vector(7 downto 0); SIGNAL SExp12, SExp12_o : std_logic_vector(7 downto 0); SIGNAL LMan12, LMan12_o : std_logic_vector(22 downto 0); SIGNAL SMan12, SMan12_o : std_logic_vector(22 downto 0); SIGNAL LSign12, LSign12_o : std_logic; SIGNAL SSign12, SSign12_o : std_logic; SIGNAL LExp23,LExp23_o : std_logic_vector(7 downto 0); SIGNAL SExp23,SExp23_o : std_logic_vector(7 downto 0); SIGNAL LMan23,LMan23_o : std_logic_vector(22 downto 0); SIGNAL SMan23,SMan23_o : std_logic_vector(22 downto 0); SIGNAL LSign23,LSign23_o : std_logic; SIGNAL SSign23,SSign23_o : std_logic; SIGNAL sdistance23,sdistance23_o : std_logic_vector(4 downto 0); SIGNAL LExp34,LExp34_o : std_logic_vector(7 DOWNTO 0); SIGNAL LMan34,LMan34_o : std_logic_vector(23 DOWNTO 0); SIGNAL SMan34,SMan34_o : std_logic_vector(23 DOWNTO 0); SIGNAL LSign34,LSign34_o : std_logic; SIGNAL SSign34,SSign34_o : std_logic; SIGNAL Exp45,Exp45_o : std_logic_vector(7 DOWNTO 0); SIGNAL LMan45,LMan45_o : std_logic_vector(23 DOWNTO 0); SIGNAL SMan45,SMan45_o : std_logic_vector(23 DOWNTO 0); SIGNAL Sign45,Sign45_o : std_logic; SIGNAL AddSub45,AddSub45_o : std_logic; SIGNAL UExp56,UExp56_o : std_logic_vector(8 DOWNTO 0); SIGNAL UMan56,UMan56_o : std_logic_vector(24 DOWNTO 0); SIGNAL ExpCor67,ExpCor67_o : std_logic_vector (7 DOWNTO 0); SIGNAL ShfDst67,ShfDst67_o : std_logic_vector (4 DOWNTO 0); SIGNAL OExp67,OExp67_o : std_logic_vector(8 DOWNTO 0); SIGNAL OMan67,OMan67_o : std_logic_vector(24 DOWNTO 0); SIGNAL Q78,Q78_o : std_logic_vector(31 DOWNTO 0); BEGIN -- Stage 1 Inst1: CompareExp_comb PORT MAP (Op_A, Op_B, LExp12, SExp12, LMan12, SMan12, LSign12, SSign12); InstR1: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(LExp12,Clk,Reset,Enable,LExp12_o); InstR2: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(SExp12,Clk,Reset,Enable,SExp12_o); InstR3: REG_GENERIC_ENABLE GENERIC MAP(23) PORT MAP(LMan12,Clk,Reset,Enable,LMan12_o); InstR4: REG_GENERIC_ENABLE GENERIC MAP(23) PORT MAP(SMan12,Clk,Reset,Enable,SMan12_o); InstR5: REG_1bit_ENABLE PORT MAP(SSign12,Clk,Reset,Enable,SSign12_o); InstR6: REG_1bit_ENABLE PORT MAP(LSign12,Clk,Reset,Enable,LSign12_o); -- Stage 2 Inst2: ComputeShift_comb PORT MAP (LExp12_o, SExp12_o, LMan12_o, SMan12_o, LSign12_o, SSign12_o, LExp23, SExp23, LMan23, SMan23, LSign23, SSign23, sdistance23); InstR7: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(LExp23,Clk,Reset,Enable,LExp23_o); InstR8: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(SExp23,Clk,Reset,Enable,SExp23_o); InstR9: REG_GENERIC_ENABLE GENERIC MAP(23) PORT MAP(LMan23,Clk,Reset,Enable,LMan23_o); InstR10: REG_GENERIC_ENABLE GENERIC MAP(23) PORT MAP(SMan23,Clk,Reset,Enable,SMan23_o); InstR11: REG_1bit_ENABLE PORT MAP(SSign23,Clk,Reset,Enable,SSign23_o); InstR12: REG_1bit_ENABLE PORT MAP(LSign23,Clk,Reset,Enable,LSign23_o); InstR13: REG_GENERIC_ENABLE GENERIC MAP(5) PORT MAP(sdistance23,Clk,Reset,Enable,sdistance23_o); --Stage 3 Inst3: ShiftMan_comb PORT MAP (sdistance23_o, LExp23_o, SExp23_o, LMan23_o, SMan23_o, LSign23_o, SSign23_o, LExp34, LMan34, SMan34, LSign34, SSign34); InstR14: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(LExp34,Clk,Reset,Enable,LExp34_o); InstR15: REG_GENERIC_ENABLE GENERIC MAP(24) PORT MAP(LMan34,Clk,Reset,Enable,LMan34_o); InstR16: REG_GENERIC_ENABLE GENERIC MAP(24) PORT MAP(SMan34,Clk,Reset,Enable,SMan34_o); InstR17: REG_1bit_ENABLE PORT MAP(SSign34,Clk,Reset,Enable,SSign34_o); InstR18: REG_1bit_ENABLE PORT MAP(LSign34,Clk,Reset,Enable,LSign34_o); --Stage 4 Inst4: CompareMan_comb PORT MAP (LSign34_o, LExp34_o, LMan34_o, SSign34_o, SMan34_o, Exp45, LMan45, SMan45, Sign45, AddSub45); InstR19: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(Exp45,Clk,Reset,Enable,Exp45_o); InstR20: REG_GENERIC_ENABLE GENERIC MAP(24) PORT MAP(LMan45,Clk,Reset,Enable,LMan45_o); InstR21: REG_GENERIC_ENABLE GENERIC MAP(24) PORT MAP(SMan45,Clk,Reset,Enable,SMan45_o); InstR22: REG_1bit_ENABLE PORT MAP(Sign45,Clk,Reset,Enable,Sign45_o); InstR23: REG_1bit_ENABLE PORT MAP(AddSub45,Clk,Reset,Enable,AddSub45_o); --Stage 5 Inst5: AddSubMan_comb PORT MAP (Sign45_o, AddSub45_o, Exp45_o, LMan45_o, SMan45_o, UExp56, UMan56); InstR24: REG_GENERIC_ENABLE GENERIC MAP(9) PORT MAP(UExp56,Clk,Reset,Enable,UExp56_o); InstR25: REG_GENERIC_ENABLE GENERIC MAP(25) PORT MAP(UMan56,Clk,Reset,Enable,UMan56_o); --Stage 6 Inst6: Norm1_comb PORT MAP (UMan56_o, UExp56_o, ExpCor67, ShfDst67, OMan67, OExp67); InstR26: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(ExpCor67,Clk,Reset,Enable,ExpCor67_o); InstR27: REG_GENERIC_ENABLE GENERIC MAP(5) PORT MAP(ShfDst67,Clk,Reset,Enable,ShfDst67_o); InstR28: REG_GENERIC_ENABLE GENERIC MAP(25) PORT MAP(OMan67,Clk,Reset,Enable,OMan67_o); InstR29: REG_GENERIC_ENABLE GENERIC MAP(9) PORT MAP(OExp67,Clk,Reset,Enable,OExp67_o); --Stage 7 Inst7: Norm2_comb PORT MAP (ExpCor67_o, ShfDst67_o, OExp67_o, OMan67_o, Q78); InstR30: REG_GENERIC_ENABLE GENERIC MAP(32) PORT MAP(Q78,Clk,Reset,Enable,Q78_o); --Stage 8 InstR31: REG_GENERIC_ENABLE GENERIC MAP(32) PORT MAP(Q78_o,Clk,Reset,Enable,Op_Q); -- Shiftregister with Enable InstSR: shiftregister generic map (8) port map (Enable,Clk,Reset,Enable,Done); END STRUCTURAL; -------------------------------------------------------------- -- Copyright 2001 by Howard University All rights reserved. -- -- Design Name : 8 stage pipelined Floating Point Subtractor -- Name : Ibrahim Sahin & Clay Gloster -- Date : March 2001 -- Description : ------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; ENTITY FpSubCore_8_hold IS PORT(clk : IN std_logic; reset : IN std_logic; Enable : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); Op_Q : OUT std_logic_vector(31 DOWNTO 0); Done : OUT std_logic); END FpSubCore_8_hold; ARCHITECTURE STRUCTURAL OF FpSubCore_8_hold IS COMPONENT SubCompareExp_comb PORT( Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); LExp : OUT std_logic_vector(7 DOWNTO 0); SExp : OUT std_logic_vector(7 DOWNTO 0); LMan : OUT std_logic_vector(22 DOWNTO 0); SMan : OUT std_logic_vector(22 DOWNTO 0); LSign : OUT std_logic; SSign : OUT std_logic); END COMPONENT; COMPONENT ComputeShift_comb PORT( LExp : IN std_logic_vector(7 DOWNTO 0); SExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(22 DOWNTO 0); SMan : IN std_logic_vector(22 DOWNTO 0); LSign : IN std_logic; SSign : IN std_logic; LExpP : OUT std_logic_vector(7 DOWNTO 0); SExpP : OUT std_logic_vector(7 DOWNTO 0); LManP : OUT std_logic_vector(22 DOWNTO 0); SManP : OUT std_logic_vector(22 DOWNTO 0); LSignP : OUT std_logic; SSignP : OUT std_logic; shiftdistance : OUT std_logic_vector(4 DOWNTO 0)); END COMPONENT; COMPONENT ShiftMan_comb PORT( shiftdistance : IN std_logic_vector(4 DOWNTO 0); LExp : IN std_logic_vector(7 DOWNTO 0); SExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(22 DOWNTO 0); SMan : IN std_logic_vector(22 DOWNTO 0); LSign : IN std_logic; SSign : IN std_logic; LExpP : OUT std_logic_vector(7 DOWNTO 0); LManP : OUT std_logic_vector(23 DOWNTO 0); SManP : OUT std_logic_vector(23 DOWNTO 0); LSignP : OUT std_logic; SSignP : OUT std_logic); END COMPONENT; COMPONENT CompareMan_comb PORT( LSign : IN std_logic; LExp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(23 DOWNTO 0); SSign : IN std_logic; SMan : IN std_logic_vector(23 DOWNTO 0); Exp : OUT std_logic_vector(7 DOWNTO 0); LMan1 : OUT std_logic_vector(23 DOWNTO 0); SMan1 : OUT std_logic_vector(23 DOWNTO 0); Sign : OUT std_logic; AddSub : OUT std_logic); END COMPONENT; COMPONENT AddSubMan_comb PORT( Sign : IN std_logic; AddSub : IN std_logic; Exp : IN std_logic_vector(7 DOWNTO 0); LMan : IN std_logic_vector(23 DOWNTO 0); SMan : IN std_logic_vector(23 DOWNTO 0); UExp : OUT std_logic_vector(8 DOWNTO 0); UMan : OUT std_logic_vector(24 DOWNTO 0)); END COMPONENT; COMPONENT Norm1_comb PORT( UMan : IN std_logic_vector(24 downto 0); UExp : IN std_logic_vector (8 DOWNTO 0); ExpCor : OUT std_logic_vector (7 DOWNTO 0); ShfDst : OUT std_logic_vector (4 DOWNTO 0); OMan : OUT std_logic_vector (24 DOWNTO 0); OExp : OUT std_logic_vector (8 DOWNTO 0)); END COMPONENT; COMPONENT Norm2_comb PORT( ExpCor : IN std_logic_vector (7 DOWNTO 0); ShfDst : IN std_logic_vector (4 DOWNTO 0); UExp : IN std_logic_vector (8 DOWNTO 0); UMan : IN std_logic_vector (24 DOWNTO 0); Q : OUT std_logic_vector(31 DOWNTO 0)); END COMPONENT; COMPONENT REG_GENERIC_ENABLE generic (Width : integer); port (Datain : in std_logic_vector(Width-1 downto 0); Clk,Reset,Enable : in std_logic; Q: out std_logic_vector(Width-1 downto 0) ); END COMPONENT; COMPONENT REG_1bit_ENABLE port (Datain : in std_logic; Clk,Reset,Enable : in std_logic; Q: out std_logic); end COMPONENT; COMPONENT shiftregister generic (Width : integer); port (Datain : in std_logic; Clk,Reset,Enable : in std_logic; Q: out std_logic); end COMPONENT; SIGNAL LExp12, LExp12_o : std_logic_vector(7 downto 0); SIGNAL SExp12, SExp12_o : std_logic_vector(7 downto 0); SIGNAL LMan12, LMan12_o : std_logic_vector(22 downto 0); SIGNAL SMan12, SMan12_o : std_logic_vector(22 downto 0); SIGNAL LSign12, LSign12_o : std_logic; SIGNAL SSign12, SSign12_o : std_logic; SIGNAL LExp23,LExp23_o : std_logic_vector(7 downto 0); SIGNAL SExp23,SExp23_o : std_logic_vector(7 downto 0); SIGNAL LMan23,LMan23_o : std_logic_vector(22 downto 0); SIGNAL SMan23,SMan23_o : std_logic_vector(22 downto 0); SIGNAL LSign23,LSign23_o : std_logic; SIGNAL SSign23,SSign23_o : std_logic; SIGNAL sdistance23,sdistance23_o : std_logic_vector(4 downto 0); SIGNAL LExp34,LExp34_o : std_logic_vector(7 DOWNTO 0); SIGNAL LMan34,LMan34_o : std_logic_vector(23 DOWNTO 0); SIGNAL SMan34,SMan34_o : std_logic_vector(23 DOWNTO 0); SIGNAL LSign34,LSign34_o : std_logic; SIGNAL SSign34,SSign34_o : std_logic; SIGNAL Exp45,Exp45_o : std_logic_vector(7 DOWNTO 0); SIGNAL LMan45,LMan45_o : std_logic_vector(23 DOWNTO 0); SIGNAL SMan45,SMan45_o : std_logic_vector(23 DOWNTO 0); SIGNAL Sign45,Sign45_o : std_logic; SIGNAL AddSub45,AddSub45_o : std_logic; SIGNAL UExp56,UExp56_o : std_logic_vector(8 DOWNTO 0); SIGNAL UMan56,UMan56_o : std_logic_vector(24 DOWNTO 0); SIGNAL ExpCor67,ExpCor67_o : std_logic_vector (7 DOWNTO 0); SIGNAL ShfDst67,ShfDst67_o : std_logic_vector (4 DOWNTO 0); SIGNAL OExp67,OExp67_o : std_logic_vector(8 DOWNTO 0); SIGNAL OMan67,OMan67_o : std_logic_vector(24 DOWNTO 0); SIGNAL Q78,Q78_o : std_logic_vector(31 DOWNTO 0); BEGIN -- Stage 1 Inst1: SubCompareExp_comb PORT MAP (Op_A, Op_B, LExp12, SExp12, LMan12, SMan12, LSign12, SSign12); InstR1: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(LExp12,Clk,Reset,Enable,LExp12_o); InstR2: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(SExp12,Clk,Reset,Enable,SExp12_o); InstR3: REG_GENERIC_ENABLE GENERIC MAP(23) PORT MAP(LMan12,Clk,Reset,Enable,LMan12_o); InstR4: REG_GENERIC_ENABLE GENERIC MAP(23) PORT MAP(SMan12,Clk,Reset,Enable,SMan12_o); InstR5: REG_1bit_ENABLE PORT MAP(SSign12,Clk,Reset,Enable,SSign12_o); InstR6: REG_1bit_ENABLE PORT MAP(LSign12,Clk,Reset,Enable,LSign12_o); -- Stage 2 Inst2: ComputeShift_comb PORT MAP (LExp12_o, SExp12_o, LMan12_o, SMan12_o, LSign12_o, SSign12_o, LExp23, SExp23, LMan23, SMan23, LSign23, SSign23, sdistance23); InstR7: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(LExp23,Clk,Reset,Enable,LExp23_o); InstR8: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(SExp23,Clk,Reset,Enable,SExp23_o); InstR9: REG_GENERIC_ENABLE GENERIC MAP(23) PORT MAP(LMan23,Clk,Reset,Enable,LMan23_o); InstR10: REG_GENERIC_ENABLE GENERIC MAP(23) PORT MAP(SMan23,Clk,Reset,Enable,SMan23_o); InstR11: REG_1bit_ENABLE PORT MAP(SSign23,Clk,Reset,Enable,SSign23_o); InstR12: REG_1bit_ENABLE PORT MAP(LSign23,Clk,Reset,Enable,LSign23_o); InstR13: REG_GENERIC_ENABLE GENERIC MAP(5) PORT MAP(sdistance23,Clk,Reset,Enable,sdistance23_o); --Stage 3 Inst3: ShiftMan_comb PORT MAP (sdistance23_o, LExp23_o, SExp23_o, LMan23_o, SMan23_o, LSign23_o, SSign23_o, LExp34, LMan34, SMan34, LSign34, SSign34); InstR14: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(LExp34,Clk,Reset,Enable,LExp34_o); InstR15: REG_GENERIC_ENABLE GENERIC MAP(24) PORT MAP(LMan34,Clk,Reset,Enable,LMan34_o); InstR16: REG_GENERIC_ENABLE GENERIC MAP(24) PORT MAP(SMan34,Clk,Reset,Enable,SMan34_o); InstR17: REG_1bit_ENABLE PORT MAP(SSign34,Clk,Reset,Enable,SSign34_o); InstR18: REG_1bit_ENABLE PORT MAP(LSign34,Clk,Reset,Enable,LSign34_o); --Stage 4 Inst4: CompareMan_comb PORT MAP (LSign34_o, LExp34_o, LMan34_o, SSign34_o, SMan34_o, Exp45, LMan45, SMan45, Sign45, AddSub45); InstR19: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(Exp45,Clk,Reset,Enable,Exp45_o); InstR20: REG_GENERIC_ENABLE GENERIC MAP(24) PORT MAP(LMan45,Clk,Reset,Enable,LMan45_o); InstR21: REG_GENERIC_ENABLE GENERIC MAP(24) PORT MAP(SMan45,Clk,Reset,Enable,SMan45_o); InstR22: REG_1bit_ENABLE PORT MAP(Sign45,Clk,Reset,Enable,Sign45_o); InstR23: REG_1bit_ENABLE PORT MAP(AddSub45,Clk,Reset,Enable,AddSub45_o); --Stage 5 Inst5: AddSubMan_comb PORT MAP (Sign45_o, AddSub45_o, Exp45_o, LMan45_o, SMan45_o, UExp56, UMan56); InstR24: REG_GENERIC_ENABLE GENERIC MAP(9) PORT MAP(UExp56,Clk,Reset,Enable,UExp56_o); InstR25: REG_GENERIC_ENABLE GENERIC MAP(25) PORT MAP(UMan56,Clk,Reset,Enable,UMan56_o); --Stage 6 Inst6: Norm1_comb PORT MAP (UMan56_o, UExp56_o, ExpCor67, ShfDst67, OMan67, OExp67); InstR26: REG_GENERIC_ENABLE GENERIC MAP(8) PORT MAP(ExpCor67,Clk,Reset,Enable,ExpCor67_o); InstR27: REG_GENERIC_ENABLE GENERIC MAP(5) PORT MAP(ShfDst67,Clk,Reset,Enable,ShfDst67_o); InstR28: REG_GENERIC_ENABLE GENERIC MAP(25) PORT MAP(OMan67,Clk,Reset,Enable,OMan67_o); InstR29: REG_GENERIC_ENABLE GENERIC MAP(9) PORT MAP(OExp67,Clk,Reset,Enable,OExp67_o); --Stage 7 Inst7: Norm2_comb PORT MAP (ExpCor67_o, ShfDst67_o, OExp67_o, OMan67_o, Q78); InstR30: REG_GENERIC_ENABLE GENERIC MAP(32) PORT MAP(Q78,Clk,Reset,Enable,Q78_o); --Stage 8 InstR31: REG_GENERIC_ENABLE GENERIC MAP(32) PORT MAP(Q78_o,Clk,Reset,Enable,Op_Q); -- Shiftregister with Enable InstSR: shiftregister generic map (8) port map (Enable,Clk,Reset,Enable,Done); END STRUCTURAL; ------------------------------------------------------------- -- Copyright 2001 by Howard University All rights reserved. -- -- Design: FFT sine cosine unit -- N = 1024 -- Name: Generated by FFTsincos program (Clay Gloster - author) -- -- Date: October 2001 -- Description: Takes as input nk which is an integer from -- 0 to N-1 and outputs sin(theta) cos(theta) -- where theta = 2*pi*nk/N -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use WORK.all; ENTITY FFTsincos_1024 IS PORT(nk : IN std_logic_vector (9 downto 0); sine, cosine : OUT std_logic_vector(31 downto 0)); --done: OUT std_logic END FFTsincos_1024; ARCHITECTURE RTL OF FFTsincos_1024 IS BEGIN PROCESS(nk) BEGIN case nk is when "0000000000" => sine <= "00000000000000000000000000000000"; cosine <= "00111111100000000000000000000000"; when "0000000001" => sine <= "00111011110010010001000101001010"; cosine <= "00111111011111111111111011000100"; when "0000000010" => sine <= "00111100010010010001000001010010"; cosine <= "00111111011111111111101100010001"; when "0000000011" => sine <= "00111100100101101100101100000111"; cosine <= "00111111011111111111010011100101"; when "0000000100" => sine <= "00111100110010010000110001110010"; cosine <= "00111111011111111110110001000011"; when "0000000101" => sine <= "00111100111110110100101111101100"; cosine <= "00111111011111111110000100101000"; when "0000000110" => sine <= "00111101000101101100010001111101"; cosine <= "00111111011111111101001110010111"; when "0000000111" => sine <= "00111101001011111110000110010000"; cosine <= "00111111011111111100001110001110"; when "0000001000" => sine <= "00111101010010001111110011110001"; cosine <= "00111111011111111011000100001110"; when "0000001001" => sine <= "00111101011000100001011001100010"; cosine <= "00111111011111111001110000010111"; when "0000001010" => sine <= "00111101011110110010110110100110"; cosine <= "00111111011111111000010010101001"; when "0000001011" => sine <= "00111101100010100010000100111110"; cosine <= "00111111011111110110101011000101"; when "0000001100" => sine <= "00111101100101101010101001010101"; cosine <= "00111111011111110100111001101010"; when "0000001101" => sine <= "00111101101000110011000111111000"; cosine <= "00111111011111110010111110011010"; when "0000001110" => sine <= "00111101101011111011100000001001"; cosine <= "00111111011111110000111001010100"; when "0000001111" => sine <= "00111101101111000011110001101000"; cosine <= "00111111011111101110101010011000"; when "0000010000" => sine <= "00111101110010001011111011110110"; cosine <= "00111111011111101100010001101000"; when "0000010001" => sine <= "00111101110101010011111110010101"; cosine <= "00111111011111101001101111000010"; when "0000010010" => sine <= "00111101111000011011111000100110"; cosine <= "00111111011111100111000010101001"; when "0000010011" => sine <= "00111101111011100011101010001001"; cosine <= "00111111011111100100001100011100"; when "0000010100" => sine <= "00111101111110101011010010100001"; cosine <= "00111111011111100001001100011011"; when "0000010101" => sine <= "00111110000000111001011000100111"; cosine <= "00111111011111011110000010100111"; when "0000010110" => sine <= "00111110000010011101000010111001"; cosine <= "00111111011111011010101111000001"; when "0000010111" => sine <= "00111110000100000000100111110111"; cosine <= "00111111011111010111010001101001"; when "0000011000" => sine <= "00111110000101100100000111010001"; cosine <= "00111111011111010011101010100000"; when "0000011001" => sine <= "00111110000111000111100000111001"; cosine <= "00111111011111001111111001100101"; when "0000011010" => sine <= "00111110001000101010110100011111"; cosine <= "00111111011111001011111110111011"; when "0000011011" => sine <= "00111110001010001110000001110011"; cosine <= "00111111011111000111111010100000"; when "0000011100" => sine <= "00111110001011110001001000100110"; cosine <= "00111111011111000011101100010111"; when "0000011101" => sine <= "00111110001101010100001000101010"; cosine <= "00111111011110111111010100011111"; when "0000011110" => sine <= "00111110001110110111000001101110"; cosine <= "00111111011110111010110010111010"; when "0000011111" => sine <= "00111110010000011001110011100100"; cosine <= "00111111011110110110000111100111"; when "0000100000" => sine <= "00111110010001111100011101111011"; cosine <= "00111111011110110001010010101001"; when "0000100001" => sine <= "00111110010011011111000000100110"; cosine <= "00111111011110101100010011111110"; when "0000100010" => sine <= "00111110010101000001011011010101"; cosine <= "00111111011110100111001011101001"; when "0000100011" => sine <= "00111110010110100011101101111001"; cosine <= "00111111011110100001111001101010"; when "0000100100" => sine <= "00111110011000000101111000000010"; cosine <= "00111111011110011100011110000010"; when "0000100101" => sine <= "00111110011001100111111001100001"; cosine <= "00111111011110010110111000110001"; when "0000100110" => sine <= "00111110011011001001110010000111"; cosine <= "00111111011110010001001001111001"; when "0000100111" => sine <= "00111110011100101011100001100110"; cosine <= "00111111011110001011010001011010"; when "0000101000" => sine <= "00111110011110001101000111101110"; cosine <= "00111111011110000101001111010110"; when "0000101001" => sine <= "00111110011111101110100100010000"; cosine <= "00111111011101111111000011101101"; when "0000101010" => sine <= "00111110100000100111111011011110"; cosine <= "00111111011101111000101110011111"; when "0000101011" => sine <= "00111110100001011000011111110011"; cosine <= "00111111011101110010001111110000"; when "0000101100" => sine <= "00111110100010001000111110111101"; cosine <= "00111111011101101011100111011110"; when "0000101101" => sine <= "00111110100010111001011000110111"; cosine <= "00111111011101100100110101101100"; when "0000101110" => sine <= "00111110100011101001101101011001"; cosine <= "00111111011101011101111010011001"; when "0000101111" => sine <= "00111110100100011001111100011010"; cosine <= "00111111011101010110110101101000"; when "0000110000" => sine <= "00111110100101001010000101110101"; cosine <= "00111111011101001111100111011010"; when "0000110001" => sine <= "00111110100101111010001001100000"; cosine <= "00111111011101001000001111101111"; when "0000110010" => sine <= "00111110100110101010000111010101"; cosine <= "00111111011101000000101110101000"; when "0000110011" => sine <= "00111110100111011001111111001101"; cosine <= "00111111011100111001000100001000"; when "0000110100" => sine <= "00111110101000001001110001000000"; cosine <= "00111111011100110001010000001110"; when "0000110101" => sine <= "00111110101000111001011100100110"; cosine <= "00111111011100101001010010111101"; when "0000110110" => sine <= "00111110101001101001000001111001"; cosine <= "00111111011100100001001100010101"; when "0000110111" => sine <= "00111110101010011000100000110001"; cosine <= "00111111011100011000111100010111"; when "0000111000" => sine <= "00111110101011000111111001000111"; cosine <= "00111111011100010000100011000110"; when "0000111001" => sine <= "00111110101011110111001010110010"; cosine <= "00111111011100001000000000100010"; when "0000111010" => sine <= "00111110101100100110010101101101"; cosine <= "00111111011011111111010100101100"; when "0000111011" => sine <= "00111110101101010101011001110000"; cosine <= "00111111011011110110011111100110"; when "0000111100" => sine <= "00111110101110000100010110110011"; cosine <= "00111111011011101101100001010010"; when "0000111101" => sine <= "00111110101110110011001100110000"; cosine <= "00111111011011100100011001110000"; when "0000111110" => sine <= "00111110101111100001111011011111"; cosine <= "00111111011011011011001001000010"; when "0000111111" => sine <= "00111110110000010000100010111000"; cosine <= "00111111011011010001101111001010"; when "0001000000" => sine <= "00111110110000111111000010110101"; cosine <= "00111111011011001000001100001000"; when "0001000001" => sine <= "00111110110001101101011011001111"; cosine <= "00111111011010111110011111111111"; when "0001000010" => sine <= "00111110110010011011101011111110"; cosine <= "00111111011010110100101010110000"; when "0001000011" => sine <= "00111110110011001001110100111011"; cosine <= "00111111011010101010101100011100"; when "0001000100" => sine <= "00111110110011110111110101111111"; cosine <= "00111111011010100000100101000110"; when "0001000101" => sine <= "00111110110100100101101111000100"; cosine <= "00111111011010010110010100101101"; when "0001000110" => sine <= "00111110110101010011100000000001"; cosine <= "00111111011010001011111011010101"; when "0001000111" => sine <= "00111110110110000001001000110000"; cosine <= "00111111011010000001011000111111"; when "0001001000" => sine <= "00111110110110101110101001001010"; cosine <= "00111111011001110110101101101011"; when "0001001001" => sine <= "00111110110111011100000001001000"; cosine <= "00111111011001101011111001011101"; when "0001001010" => sine <= "00111110111000001001010000100011"; cosine <= "00111111011001100000111100010110"; when "0001001011" => sine <= "00111110111000110110010111010011"; cosine <= "00111111011001010101110110010110"; when "0001001100" => sine <= "00111110111001100011010101010010"; cosine <= "00111111011001001010100111100001"; when "0001001101" => sine <= "00111110111010010000001010011010"; cosine <= "00111111011000111111001111110111"; when "0001001110" => sine <= "00111110111010111100110110100010"; cosine <= "00111111011000110011101111011011"; when "0001001111" => sine <= "00111110111011101001011001100100"; cosine <= "00111111011000101000000110001110"; when "0001010000" => sine <= "00111110111100010101110011011010"; cosine <= "00111111011000011100010100010011"; when "0001010001" => sine <= "00111110111101000010000011111100"; cosine <= "00111111011000010000011001101010"; when "0001010010" => sine <= "00111110111101101110001011000100"; cosine <= "00111111011000000100010110010110"; when "0001010011" => sine <= "00111110111110011010001000101011"; cosine <= "00111111010111111000001010011001"; when "0001010100" => sine <= "00111110111111000101111100101001"; cosine <= "00111111010111101011110101110100"; when "0001010101" => sine <= "00111110111111110001100110111001"; cosine <= "00111111010111011111011000101001"; when "0001010110" => sine <= "00111111000000001110100011101010"; cosine <= "00111111010111010010110010111011"; when "0001010111" => sine <= "00111111000000100100001110111001"; cosine <= "00111111010111000110000100101011"; when "0001011000" => sine <= "00111111000000111001110101000110"; cosine <= "00111111010110111001001101111011"; when "0001011001" => sine <= "00111111000001001111010110001111"; cosine <= "00111111010110101100001110101101"; when "0001011010" => sine <= "00111111000001100100110010010000"; cosine <= "00111111010110011111000111000100"; when "0001011011" => sine <= "00111111000001111010001001000101"; cosine <= "00111111010110010001110111000000"; when "0001011100" => sine <= "00111111000010001111011010101100"; cosine <= "00111111010110000100011110100101"; when "0001011101" => sine <= "00111111000010100100100111000001"; cosine <= "00111111010101110110111101110101"; when "0001011110" => sine <= "00111111000010111001101110000000"; cosine <= "00111111010101101001010100110001"; when "0001011111" => sine <= "00111111000011001110101111100111"; cosine <= "00111111010101011011100011011011"; when "0001100000" => sine <= "00111111000011100011101011110011"; cosine <= "00111111010101001101101001110101"; when "0001100001" => sine <= "00111111000011111000100010011111"; cosine <= "00111111010100111111101000000011"; when "0001100010" => sine <= "00111111000100001101010011101001"; cosine <= "00111111010100110001011110000110"; when "0001100011" => sine <= "00111111000100100001111111001110"; cosine <= "00111111010100100011001100000000"; when "0001100100" => sine <= "00111111000100110110100101001010"; cosine <= "00111111010100010100110001110010"; when "0001100101" => sine <= "00111111000101001011000101011010"; cosine <= "00111111010100000110001111100001"; when "0001100110" => sine <= "00111111000101011111011111111100"; cosine <= "00111111010011110111100101001101"; when "0001100111" => sine <= "00111111000101110011110100101011"; cosine <= "00111111010011101000110010111010"; when "0001101000" => sine <= "00111111000110001000000011100110"; cosine <= "00111111010011011001111000101001"; when "0001101001" => sine <= "00111111000110011100001100101000"; cosine <= "00111111010011001010110110011011"; when "0001101010" => sine <= "00111111000110110000001111101110"; cosine <= "00111111010010111011101100010110"; when "0001101011" => sine <= "00111111000111000100001100110110"; cosine <= "00111111010010101100011010011001"; when "0001101100" => sine <= "00111111000111011000000011111101"; cosine <= "00111111010010011101000000101001"; when "0001101101" => sine <= "00111111000111101011110100111111"; cosine <= "00111111010010001101011111000110"; when "0001101110" => sine <= "00111111000111111111011111111001"; cosine <= "00111111010001111101110101110011"; when "0001101111" => sine <= "00111111001000010011000100101000"; cosine <= "00111111010001101110000100110100"; when "0001110000" => sine <= "00111111001000100110100011001010"; cosine <= "00111111010001011110001100001010"; when "0001110001" => sine <= "00111111001000111001111011011011"; cosine <= "00111111010001001110001011110111"; when "0001110010" => sine <= "00111111001001001101001101011000"; cosine <= "00111111010000111110000011111110"; when "0001110011" => sine <= "00111111001001100000011000111110"; cosine <= "00111111010000101101110100100010"; when "0001110100" => sine <= "00111111001001110011011110001011"; cosine <= "00111111010000011101011101100110"; when "0001110101" => sine <= "00111111001010000110011100111011"; cosine <= "00111111010000001100111111001011"; when "0001110110" => sine <= "00111111001010011001010101001100"; cosine <= "00111111001111111100011001010100"; when "0001110111" => sine <= "00111111001010101100000110111010"; cosine <= "00111111001111101011101100000100"; when "0001111000" => sine <= "00111111001010111110110010000010"; cosine <= "00111111001111011010110111011110"; when "0001111001" => sine <= "00111111001011010001010110100011"; cosine <= "00111111001111001001111011100011"; when "0001111010" => sine <= "00111111001011100011110100011000"; cosine <= "00111111001110111000111000010111"; when "0001111011" => sine <= "00111111001011110110001011100000"; cosine <= "00111111001110100111101101111100"; when "0001111100" => sine <= "00111111001100001000011011110111"; cosine <= "00111111001110010110011100010101"; when "0001111101" => sine <= "00111111001100011010100101011010"; cosine <= "00111111001110000101000011100101"; when "0001111110" => sine <= "00111111001100101100101000000110"; cosine <= "00111111001101110011100011101101"; when "0001111111" => sine <= "00111111001100111110100011111010"; cosine <= "00111111001101100001111100110001"; when "0010000000" => sine <= "00111111001101010000011000110010"; cosine <= "00111111001101010000001110110101"; when "0010000001" => sine <= "00111111001101100010000110101010"; cosine <= "00111111001100111110011001111001"; when "0010000010" => sine <= "00111111001101110011101101100010"; cosine <= "00111111001100101100011110000010"; when "0010000011" => sine <= "00111111001110000101001101010101"; cosine <= "00111111001100011010011011010001"; when "0010000100" => sine <= "00111111001110010110100110000010"; cosine <= "00111111001100001000010001101010"; when "0010000101" => sine <= "00111111001110100111110111100101"; cosine <= "00111111001011110110000001010000"; when "0010000110" => sine <= "00111111001110111001000001111100"; cosine <= "00111111001011100011101010000101"; when "0010000111" => sine <= "00111111001111001010000101000100"; cosine <= "00111111001011010001001100001100"; when "0010001000" => sine <= "00111111001111011011000000111010"; cosine <= "00111111001010111110100111100111"; when "0010001001" => sine <= "00111111001111101011110101011101"; cosine <= "00111111001010101011111100011011"; when "0010001010" => sine <= "00111111001111111100100010101001"; cosine <= "00111111001010011001001010101001"; when "0010001011" => sine <= "00111111010000001101001000011011"; cosine <= "00111111001010000110010010010101"; when "0010001100" => sine <= "00111111010000011101100110110010"; cosine <= "00111111001001110011010011100001"; when "0010001101" => sine <= "00111111010000101101111101101010"; cosine <= "00111111001001100000001110010001"; when "0010001110" => sine <= "00111111010000111110001101000010"; cosine <= "00111111001001001101000010100111"; when "0010001111" => sine <= "00111111010001001110010100110110"; cosine <= "00111111001000111001110000100110"; when "0010010000" => sine <= "00111111010001011110010101000101"; cosine <= "00111111001000100110011000010010"; when "0010010001" => sine <= "00111111010001101110001101101011"; cosine <= "00111111001000010010111001101100"; when "0010010010" => sine <= "00111111010001111101111110100110"; cosine <= "00111111000111111111010100111010"; when "0010010011" => sine <= "00111111010010001101100111110100"; cosine <= "00111111000111101011101001111100"; when "0010010100" => sine <= "00111111010010011101001001010011"; cosine <= "00111111000111010111111000110111"; when "0010010101" => sine <= "00111111010010101100100010111111"; cosine <= "00111111000111000100000001101101"; when "0010010110" => sine <= "00111111010010111011110100110111"; cosine <= "00111111000110110000000100100001"; when "0010010111" => sine <= "00111111010011001010111110111000"; cosine <= "00111111000110011100000001011000"; when "0010011000" => sine <= "00111111010011011010000001000001"; cosine <= "00111111000110000111111000010011"; when "0010011001" => sine <= "00111111010011101000111011001110"; cosine <= "00111111000101110011101001010100"; when "0010011010" => sine <= "00111111010011110111101101011101"; cosine <= "00111111000101011111010100100010"; when "0010011011" => sine <= "00111111010100000110010111101100"; cosine <= "00111111000101001010111001111101"; when "0010011100" => sine <= "00111111010100010100111001111001"; cosine <= "00111111000100110110011001101010"; when "0010011101" => sine <= "00111111010100100011010100000001"; cosine <= "00111111000100100001110011101011"; when "0010011110" => sine <= "00111111010100110001100110000011"; cosine <= "00111111000100001101001000000010"; when "0010011111" => sine <= "00111111010100111111101111111100"; cosine <= "00111111000011111000010110110101"; when "0010100000" => sine <= "00111111010101001101110001101010"; cosine <= "00111111000011100011100000000110"; when "0010100001" => sine <= "00111111010101011011101011001011"; cosine <= "00111111000011001110100011111000"; when "0010100010" => sine <= "00111111010101101001011100011100"; cosine <= "00111111000010111001100010001101"; when "0010100011" => sine <= "00111111010101110111000101011011"; cosine <= "00111111000010100100011011001011"; when "0010100100" => sine <= "00111111010110000100100110000111"; cosine <= "00111111000010001111001110110100"; when "0010100101" => sine <= "00111111010110010001111110011110"; cosine <= "00111111000001111001111101001010"; when "0010100110" => sine <= "00111111010110011111001110011100"; cosine <= "00111111000001100100100110010001"; when "0010100111" => sine <= "00111111010110101100010110000001"; cosine <= "00111111000001001111001010001110"; when "0010101000" => sine <= "00111111010110111001010101001010"; cosine <= "00111111000000111001101001000010"; when "0010101001" => sine <= "00111111010111000110001011110101"; cosine <= "00111111000000100100000010110001"; when "0010101010" => sine <= "00111111010111010010111010000000"; cosine <= "00111111000000001110010111100000"; when "0010101011" => sine <= "00111111010111011111011111101010"; cosine <= "00111110111111110001001110011111"; when "0010101100" => sine <= "00111111010111101011111100110000"; cosine <= "00111110111111000101100100001011"; when "0010101101" => sine <= "00111111010111111000010001010000"; cosine <= "00111110111110011001110000000110"; when "0010101110" => sine <= "00111111011000000100011101001000"; cosine <= "00111110111101101101110010011001"; when "0010101111" => sine <= "00111111011000010000100000010111"; cosine <= "00111110111101000001101011001110"; when "0010110000" => sine <= "00111111011000011100011010111011"; cosine <= "00111110111100010101011010100101"; when "0010110001" => sine <= "00111111011000101000001100110010"; cosine <= "00111110111011101001000000101101"; when "0010110010" => sine <= "00111111011000110011110101111010"; cosine <= "00111110111010111100011101100100"; when "0010110011" => sine <= "00111111011000111111010110010001"; cosine <= "00111110111010001111110001010101"; when "0010110100" => sine <= "00111111011001001010101101110110"; cosine <= "00111110111001100010111100001011"; when "0010110101" => sine <= "00111111011001010101111100100110"; cosine <= "00111110111000110101111110000101"; when "0010110110" => sine <= "00111111011001100001000010100000"; cosine <= "00111110111000001000110111001110"; when "0010110111" => sine <= "00111111011001101011111111100011"; cosine <= "00111110110111011011100111110001"; when "0010111000" => sine <= "00111111011001110110110011101100"; cosine <= "00111110110110101110001111101101"; when "0010111001" => sine <= "00111111011010000001011110111011"; cosine <= "00111110110110000000101111010001"; when "0010111010" => sine <= "00111111011010001100000001001100"; cosine <= "00111110110101010011000110011100"; when "0010111011" => sine <= "00111111011010010110011010011111"; cosine <= "00111110110100100101010101011000"; when "0010111100" => sine <= "00111111011010100000101010110011"; cosine <= "00111110110011110111011100010010"; when "0010111101" => sine <= "00111111011010101010110010000100"; cosine <= "00111110110011001001011011001000"; when "0010111110" => sine <= "00111111011010110100110000010011"; cosine <= "00111110110010011011010010001000"; when "0010111111" => sine <= "00111111011010111110100101011101"; cosine <= "00111110110001101101000001010011"; when "0011000000" => sine <= "00111111011011001000010001100001"; cosine <= "00111110110000111110101000110100"; when "0011000001" => sine <= "00111111011011010001110100011101"; cosine <= "00111110110000010000001000110101"; when "0011000010" => sine <= "00111111011011011011001110010000"; cosine <= "00111110101111100001100001010110"; when "0011000011" => sine <= "00111111011011100100011110111001"; cosine <= "00111110101110110010110010100101"; when "0011000100" => sine <= "00111111011011101101100110010110"; cosine <= "00111110101110000011111100100011"; when "0011000101" => sine <= "00111111011011110110100100100101"; cosine <= "00111110101101010100111111011011"; when "0011000110" => sine <= "00111111011011111111011001100110"; cosine <= "00111110101100100101111011010110"; when "0011000111" => sine <= "00111111011100001000000101010110"; cosine <= "00111110101011110110110000010110"; when "0011001000" => sine <= "00111111011100010000100111110101"; cosine <= "00111110101011000111011110100101"; when "0011001001" => sine <= "00111111011100011001000001000001"; cosine <= "00111110101010011000000110001110"; when "0011001010" => sine <= "00111111011100100001010000111001"; cosine <= "00111110101001101000100111010001"; when "0011001011" => sine <= "00111111011100101001010111011100"; cosine <= "00111110101000111001000001111101"; when "0011001100" => sine <= "00111111011100110001010100101000"; cosine <= "00111110101000001001010110010010"; when "0011001101" => sine <= "00111111011100111001001000011101"; cosine <= "00111110100111011001100100011010"; when "0011001110" => sine <= "00111111011101000000110010111000"; cosine <= "00111110100110101001101100100001"; when "0011001111" => sine <= "00111111011101001000010011111001"; cosine <= "00111110100101111001101110100111"; when "0011010000" => sine <= "00111111011101001111101011011111"; cosine <= "00111110100101001001101010111011"; when "0011010001" => sine <= "00111111011101010110111001101000"; cosine <= "00111110100100011001100001011100"; when "0011010010" => sine <= "00111111011101011101111110010100"; cosine <= "00111110100011101001010010010110"; when "0011010011" => sine <= "00111111011101100100111001100001"; cosine <= "00111110100010111000111101110100"; when "0011010100" => sine <= "00111111011101101011101011001110"; cosine <= "00111110100010001000100011110101"; when "0011010101" => sine <= "00111111011101110010010011011010"; cosine <= "00111110100001011000000100100110"; when "0011010110" => sine <= "00111111011101111000110010000101"; cosine <= "00111110100000100111100000010001"; when "0011010111" => sine <= "00111111011101111111000111001101"; cosine <= "00111110011111101101101101101101"; when "0011011000" => sine <= "00111111011110000101010010110000"; cosine <= "00111110011110001100010001001011"; when "0011011001" => sine <= "00111111011110001011010100110000"; cosine <= "00111110011100101010101010111011"; when "0011011010" => sine <= "00111111011110010001001101001001"; cosine <= "00111110011011001000111011010100"; when "0011011011" => sine <= "00111111011110010110111011111100"; cosine <= "00111110011001100111000010101101"; when "0011011100" => sine <= "00111111011110011100100001000111"; cosine <= "00111110011000000101000001000110"; when "0011011101" => sine <= "00111111011110100001111100101010"; cosine <= "00111110010110100010110110111101"; when "0011011110" => sine <= "00111111011110100111001110100100"; cosine <= "00111110010101000000100100010010"; when "0011011111" => sine <= "00111111011110101100010110110011"; cosine <= "00111110010011011110001001011011"; when "0011100000" => sine <= "00111111011110110001010101011000"; cosine <= "00111110010001111011100110110001"; when "0011100001" => sine <= "00111111011110110110001010010010"; cosine <= "00111110010000011000111100010010"; when "0011100010" => sine <= "00111111011110111010110101011111"; cosine <= "00111110001110110110001010011101"; when "0011100011" => sine <= "00111111011110111111010110111111"; cosine <= "00111110001101010011010001010001"; when "0011100100" => sine <= "00111111011111000011101110110001"; cosine <= "00111110001011110000010001000111"; when "0011100101" => sine <= "00111111011111000111111100110101"; cosine <= "00111110001010001101001010010101"; when "0011100110" => sine <= "00111111011111001100000001001010"; cosine <= "00111110001000101001111100111010"; when "0011100111" => sine <= "00111111011111001111111011101111"; cosine <= "00111110000111000110101001001110"; when "0011101000" => sine <= "00111111011111010011101100100100"; cosine <= "00111110000101100011001111101000"; when "0011101001" => sine <= "00111111011111010111010011101000"; cosine <= "00111110000011111111110000000111"; when "0011101010" => sine <= "00111111011111011010110000111010"; cosine <= "00111110000010011100001011001011"; when "0011101011" => sine <= "00111111011111011110000100011011"; cosine <= "00111110000000111000100000110011"; when "0011101100" => sine <= "00111111011111100001001110001001"; cosine <= "00111101111110101001100010101110"; when "0011101101" => sine <= "00111111011111100100001110000100"; cosine <= "00111101111011100001111010011010"; when "0011101110" => sine <= "00111111011111100111000100001100"; cosine <= "00111101111000011010001000101011"; when "0011101111" => sine <= "00111111011111101001110000100000"; cosine <= "00111101110101010010001110011111"; when "0011110000" => sine <= "00111111011111101100010011000000"; cosine <= "00111101110010001010001011110110"; when "0011110001" => sine <= "00111111011111101110101011101011"; cosine <= "00111101101111000010000001011101"; when "0011110010" => sine <= "00111111011111110000111010100001"; cosine <= "00111101101011111001110000000100"; when "0011110011" => sine <= "00111111011111110010111111100010"; cosine <= "00111101101000110001010111101010"; when "0011110100" => sine <= "00111111011111110100111010101101"; cosine <= "00111101100101101000111000111101"; when "0011110101" => sine <= "00111111011111110110101100000001"; cosine <= "00111101100010100000010100101101"; when "0011110110" => sine <= "00111111011111111000010011100000"; cosine <= "00111101011110101111010101110001"; when "0011110111" => sine <= "00111111011111111001110001001000"; cosine <= "00111101011000011101111000111100"; when "0011111000" => sine <= "00111111011111111011000100111010"; cosine <= "00111101010010001100010010111010"; when "0011111001" => sine <= "00111111011111111100001110110100"; cosine <= "00111101001011111010100101001000"; when "0011111010" => sine <= "00111111011111111101001110111000"; cosine <= "00111101000101101000110001000101"; when "0011111011" => sine <= "00111111011111111110000101000100"; cosine <= "00111100111110101101101101011110"; when "0011111100" => sine <= "00111111011111111110110001011001"; cosine <= "00111100110010001001110000000110"; when "0011111101" => sine <= "00111111011111111111010011110110"; cosine <= "00111100100101100101101001111111"; when "0011111110" => sine <= "00111111011111111111101100011100"; cosine <= "00111100010010000010111100001011"; when "0011111111" => sine <= "00111111011111111111111011001010"; cosine <= "00111011110001110100111101010010"; when "0100000000" => sine <= "00111111100000000000000000000000"; cosine <= "10111000011000010010111011101111"; when "0100000001" => sine <= "00111111011111111111111010111111"; cosine <= "10111011110010101101001100001001"; when "0100000010" => sine <= "00111111011111111111101100000110"; cosine <= "10111100010010011111000101100000"; when "0100000011" => sine <= "00111111011111111111010011010101"; cosine <= "10111100100101110011101110100100"; when "0100000100" => sine <= "00111111011111111110110000101101"; cosine <= "10111100110010010111110011100100"; when "0100000101" => sine <= "00111111011111111110000100001101"; cosine <= "10111100111110111011110001110010"; when "0100000110" => sine <= "00111111011111111101001101110110"; cosine <= "10111101000101101111110011001001"; when "0100000111" => sine <= "00111111011111111100001101100111"; cosine <= "10111101001100000001100111000101"; when "0100001000" => sine <= "00111111011111111011000011100010"; cosine <= "10111101010010010011010100101111"; when "0100001001" => sine <= "00111111011111111001101111100101"; cosine <= "10111101011000100100111010001000"; when "0100001010" => sine <= "00111111011111111000010001110010"; cosine <= "10111101011110110110010111010010"; when "0100001011" => sine <= "00111111011111110110101010001000"; cosine <= "10111101100010100011110101011000"; when "0100001100" => sine <= "00111111011111110100111000101000"; cosine <= "10111101100101101100011001100010"; when "0100001101" => sine <= "00111111011111110010111101010010"; cosine <= "10111101101000110100111000001000"; when "0100001110" => sine <= "00111111011111110000111000000110"; cosine <= "10111101101011111101010000001011"; when "0100001111" => sine <= "00111111011111101110101001000101"; cosine <= "10111101101111000101100001101100"; when "0100010000" => sine <= "00111111011111101100010000001111"; cosine <= "10111101110010001101101011111100"; when "0100010001" => sine <= "00111111011111101001101101100101"; cosine <= "10111101110101010101101110001101"; when "0100010010" => sine <= "00111111011111100111000001000110"; cosine <= "10111101111000011101101000011111"; when "0100010011" => sine <= "00111111011111100100001010110011"; cosine <= "10111101111011100101011010000100"; when "0100010100" => sine <= "00111111011111100001001010101101"; cosine <= "10111101111110101101000010001101"; when "0100010101" => sine <= "00111111011111011110000000110100"; cosine <= "10111110000000111010010000011101"; when "0100010110" => sine <= "00111111011111011010101101001000"; cosine <= "10111110000010011101111010101000"; when "0100010111" => sine <= "00111111011111010111001111101010"; cosine <= "10111110000100000001011111100101"; when "0100011000" => sine <= "00111111011111010011101000011011"; cosine <= "10111110000101100100111111000000"; when "0100011001" => sine <= "00111111011111001111110111011100"; cosine <= "10111110000111001000011000011111"; when "0100011010" => sine <= "00111111011111001011111100101100"; cosine <= "10111110001000101011101100000100"; when "0100011011" => sine <= "00111111011111000111111000001100"; cosine <= "10111110001010001110111001010000"; when "0100011100" => sine <= "00111111011111000011101001111101"; cosine <= "10111110001011110010000000000011"; when "0100011101" => sine <= "00111111011110111111010010000000"; cosine <= "10111110001101010101000000000110"; when "0100011110" => sine <= "00111111011110111010110000010101"; cosine <= "10111110001110110111111001000001"; when "0100011111" => sine <= "00111111011110110110000100111101"; cosine <= "10111110010000011010101010110110"; when "0100100000" => sine <= "00111111011110110001001111111001"; cosine <= "10111110010001111101010101000100"; when "0100100001" => sine <= "00111111011110101100010001001001"; cosine <= "10111110010011011111110111101110"; when "0100100010" => sine <= "00111111011110100111001000101111"; cosine <= "10111110010101000010010010011011"; when "0100100011" => sine <= "00111111011110100001110110101010"; cosine <= "10111110010110100100100100110101"; when "0100100100" => sine <= "00111111011110011100011010111100"; cosine <= "10111110011000000110101110111100"; when "0100100101" => sine <= "00111111011110010110110101100110"; cosine <= "10111110011001101000110000011010"; when "0100100110" => sine <= "00111111011110010001000110101001"; cosine <= "10111110011011001010101000110111"; when "0100100111" => sine <= "00111111011110001011001110000101"; cosine <= "10111110011100101100011000010011"; when "0100101000" => sine <= "00111111011110000101001011111011"; cosine <= "10111110011110001101111110010001"; when "0100101001" => sine <= "00111111011101111111000000001100"; cosine <= "10111110011111101111011010110000"; when "0100101010" => sine <= "00111111011101111000101010111010"; cosine <= "10111110100000101000010110101101"; when "0100101011" => sine <= "00111111011101110010001100000101"; cosine <= "10111110100001011000111010111100"; when "0100101100" => sine <= "00111111011101101011100011101110"; cosine <= "10111110100010001001011010000110"; when "0100101101" => sine <= "00111111011101100100110001110110"; cosine <= "10111110100010111001110011111010"; when "0100101110" => sine <= "00111111011101011101110110011110"; cosine <= "10111110100011101010001000011010"; when "0100101111" => sine <= "00111111011101010110110001101000"; cosine <= "10111110100100011010010111011010"; when "0100110000" => sine <= "00111111011101001111100011010100"; cosine <= "10111110100101001010100000101111"; when "0100110001" => sine <= "00111111011101001000001011100100"; cosine <= "10111110100101111010100100011001"; when "0100110010" => sine <= "00111111011101000000101010011000"; cosine <= "10111110100110101010100010001100"; when "0100110011" => sine <= "00111111011100111000111111110010"; cosine <= "10111110100111011010011001111110"; when "0100110100" => sine <= "00111111011100110001001011110100"; cosine <= "10111110101000001010001011101111"; when "0100110101" => sine <= "00111111011100101001001110011101"; cosine <= "10111110101000111001110111010000"; when "0100110110" => sine <= "00111111011100100001000111110000"; cosine <= "10111110101001101001011100100000"; when "0100110111" => sine <= "00111111011100011000110111101101"; cosine <= "10111110101010011000111011010110"; when "0100111000" => sine <= "00111111011100010000011110010110"; cosine <= "10111110101011001000010011100110"; when "0100111001" => sine <= "00111111011100000111111011101101"; cosine <= "10111110101011110111100101001111"; when "0100111010" => sine <= "00111111011011111111001111110010"; cosine <= "10111110101100100110110000000100"; when "0100111011" => sine <= "00111111011011110110011010100111"; cosine <= "10111110101101010101110100000100"; when "0100111100" => sine <= "00111111011011101101011100001110"; cosine <= "10111110101110000100110001000101"; when "0100111101" => sine <= "00111111011011100100010100100111"; cosine <= "10111110101110110011100110111011"; when "0100111110" => sine <= "00111111011011011011000011110100"; cosine <= "10111110101111100010010101100111"; when "0100111111" => sine <= "00111111011011010001101001110110"; cosine <= "10111110110000010000111100111010"; when "0101000000" => sine <= "00111111011011001000000110110000"; cosine <= "10111110110000111111011100110101"; when "0101000001" => sine <= "00111111011010111110011010100010"; cosine <= "10111110110001101101110101001100"; when "0101000010" => sine <= "00111111011010110100100101001101"; cosine <= "10111110110010011100000101110100"; when "0101000011" => sine <= "00111111011010101010100110110101"; cosine <= "10111110110011001010001110101110"; when "0101000100" => sine <= "00111111011010100000011111011001"; cosine <= "10111110110011111000001111110000"; when "0101000101" => sine <= "00111111011010010110001110111011"; cosine <= "10111110110100100110001000101101"; when "0101000110" => sine <= "00111111011010001011110101011110"; cosine <= "10111110110101010011111001100111"; when "0101000111" => sine <= "00111111011010000001010011000011"; cosine <= "10111110110110000001100010010011"; when "0101001000" => sine <= "00111111011001110110100111101010"; cosine <= "10111110110110101111000010100011"; when "0101001001" => sine <= "00111111011001101011110011010111"; cosine <= "10111110110111011100011010011101"; when "0101001010" => sine <= "00111111011001100000110110001010"; cosine <= "10111110111000001001101001110100"; when "0101001011" => sine <= "00111111011001010101110000000110"; cosine <= "10111110111000110110110000100001"; when "0101001100" => sine <= "00111111011001001010100001001100"; cosine <= "10111110111001100011101110011101"; when "0101001101" => sine <= "00111111011000111111001001011101"; cosine <= "10111110111010010000100011100001"; when "0101001110" => sine <= "00111111011000110011101000111101"; cosine <= "10111110111010111101001111011110"; when "0101001111" => sine <= "00111111011000100111111111101011"; cosine <= "10111110111011101001110010011101"; when "0101010000" => sine <= "00111111011000011100001101101010"; cosine <= "10111110111100010110001100001111"; when "0101010001" => sine <= "00111111011000010000010010111101"; cosine <= "10111110111101000010011100101101"; when "0101010010" => sine <= "00111111011000000100001111100100"; cosine <= "10111110111101101110100011110001"; when "0101010011" => sine <= "00111111010111111000000011100010"; cosine <= "10111110111110011010100001001100"; when "0101010100" => sine <= "00111111010111101011101110111000"; cosine <= "10111110111111000110010101000111"; when "0101010101" => sine <= "00111111010111011111010001101000"; cosine <= "10111110111111110001111111010010"; when "0101010110" => sine <= "00111111010111010010101011110101"; cosine <= "10111111000000001110101111110100"; when "0101010111" => sine <= "00111111010111000101111101100001"; cosine <= "10111111000000100100011011000001"; when "0101011000" => sine <= "00111111010110111001000110101100"; cosine <= "10111111000000111010000001001001"; when "0101011001" => sine <= "00111111010110101100000111011010"; cosine <= "10111111000001001111100010010000"; when "0101011010" => sine <= "00111111010110011110111111101011"; cosine <= "10111111000001100100111110001110"; when "0101011011" => sine <= "00111111010110010001101111100100"; cosine <= "10111111000001111010010101000010"; when "0101011100" => sine <= "00111111010110000100010111000100"; cosine <= "10111111000010001111100110100110"; when "0101011101" => sine <= "00111111010101110110110110001110"; cosine <= "10111111000010100100110010110101"; when "0101011110" => sine <= "00111111010101101001001101000110"; cosine <= "10111111000010111001111001110010"; when "0101011111" => sine <= "00111111010101011011011011101011"; cosine <= "10111111000011001110111011010111"; when "0101100000" => sine <= "00111111010101001101100010000001"; cosine <= "10111111000011100011110111100000"; when "0101100001" => sine <= "00111111010100111111100000001010"; cosine <= "10111111000011111000101110001010"; when "0101100010" => sine <= "00111111010100110001010110001000"; cosine <= "10111111000100001101011111001110"; when "0101100011" => sine <= "00111111010100100011000011111101"; cosine <= "10111111000100100010001010110000"; when "0101100100" => sine <= "00111111010100010100101001101100"; cosine <= "10111111000100110110110000101010"; when "0101100101" => sine <= "00111111010100000110000111010110"; cosine <= "10111111000101001011010000111000"; when "0101100110" => sine <= "00111111010011110111011100111110"; cosine <= "10111111000101011111101011010111"; when "0101100111" => sine <= "00111111010011101000101010100110"; cosine <= "10111111000101110100000000000000"; when "0101101000" => sine <= "00111111010011011001110000010000"; cosine <= "10111111000110001000001110111000"; when "0101101001" => sine <= "00111111010011001010101101111111"; cosine <= "10111111000110011100010111110111"; when "0101101010" => sine <= "00111111010010111011100011110101"; cosine <= "10111111000110110000011010111011"; when "0101101011" => sine <= "00111111010010101100010001110100"; cosine <= "10111111000111000100011000000000"; when "0101101100" => sine <= "00111111010010011100110111111111"; cosine <= "10111111000111011000001111000100"; when "0101101101" => sine <= "00111111010010001101010110010111"; cosine <= "10111111000111101100000000000000"; when "0101101110" => sine <= "00111111010001111101101101000001"; cosine <= "10111111000111111111101010110111"; when "0101101111" => sine <= "00111111010001101101111011111101"; cosine <= "10111111001000010011001111100100"; when "0101110000" => sine <= "00111111010001011110000011001110"; cosine <= "10111111001000100110101110000011"; when "0101110001" => sine <= "00111111010001001110000010110111"; cosine <= "10111111001000111010000110010000"; when "0101110010" => sine <= "00111111010000111101111010111011"; cosine <= "10111111001001001101011000001000"; when "0101110011" => sine <= "00111111010000101101101011011010"; cosine <= "10111111001001100000100011101011"; when "0101110100" => sine <= "00111111010000011101010100011010"; cosine <= "10111111001001110011101000110101"; when "0101110101" => sine <= "00111111010000001100110101111011"; cosine <= "10111111001010000110100111100010"; when "0101110110" => sine <= "00111111001111111100010000000000"; cosine <= "10111111001010011001011111101111"; when "0101110111" => sine <= "00111111001111101011100010101100"; cosine <= "10111111001010101100010001010111"; when "0101111000" => sine <= "00111111001111011010101110000001"; cosine <= "10111111001010111110111100011101"; when "0101111001" => sine <= "00111111001111001001110010000010"; cosine <= "10111111001011010001100000111010"; when "0101111010" => sine <= "00111111001110111000101110110010"; cosine <= "10111111001011100011111110101101"; when "0101111011" => sine <= "00111111001110100111100100010011"; cosine <= "10111111001011110110010101110001"; when "0101111100" => sine <= "00111111001110010110010010101000"; cosine <= "10111111001100001000100110000001"; when "0101111101" => sine <= "00111111001110000100111001110100"; cosine <= "10111111001100011010101111100001"; when "0101111110" => sine <= "00111111001101110011011001111000"; cosine <= "10111111001100101100110010001011"; when "0101111111" => sine <= "00111111001101100001110010111001"; cosine <= "10111111001100111110101101111011"; when "0110000000" => sine <= "00111111001101010000000100111000"; cosine <= "10111111001101010000100010101111"; when "0110000001" => sine <= "00111111001100111110001111111001"; cosine <= "10111111001101100010010000100010"; when "0110000010" => sine <= "00111111001100101100010011111101"; cosine <= "10111111001101110011110111010110"; when "0110000011" => sine <= "00111111001100011010010001001001"; cosine <= "10111111001110000101010111000110"; when "0110000100" => sine <= "00111111001100001000000111011110"; cosine <= "10111111001110010110101111101111"; when "0110000101" => sine <= "00111111001011110101110111000000"; cosine <= "10111111001110101000000001001111"; when "0110000110" => sine <= "00111111001011100011011111110001"; cosine <= "10111111001110111001001011011111"; when "0110000111" => sine <= "00111111001011010001000001110100"; cosine <= "10111111001111001010001110100100"; when "0110001000" => sine <= "00111111001010111110011101001100"; cosine <= "10111111001111011011001010010111"; when "0110001001" => sine <= "00111111001010101011110001111100"; cosine <= "10111111001111101011111110110110"; when "0110001010" => sine <= "00111111001010011001000000000110"; cosine <= "10111111001111111100101011111110"; when "0110001011" => sine <= "00111111001010000110000111101110"; cosine <= "10111111010000001101010001101101"; when "0110001100" => sine <= "00111111001001110011001000110111"; cosine <= "10111111010000011101101111111101"; when "0110001101" => sine <= "00111111001001100000000011100011"; cosine <= "10111111010000101110000110110010"; when "0110001110" => sine <= "00111111001001001100110111110110"; cosine <= "10111111010000111110010110000110"; when "0110001111" => sine <= "00111111001000111001100101110001"; cosine <= "10111111010001001110011101110110"; when "0110010000" => sine <= "00111111001000100110001101011001"; cosine <= "10111111010001011110011110000001"; when "0110010001" => sine <= "00111111001000010010101110110001"; cosine <= "10111111010001101110010110100001"; when "0110010010" => sine <= "00111111000111111111001001111011"; cosine <= "10111111010001111110000111011000"; when "0110010011" => sine <= "00111111000111101011011110111010"; cosine <= "10111111010010001101110000100010"; when "0110010100" => sine <= "00111111000111010111101101110001"; cosine <= "10111111010010011101010001111101"; when "0110010101" => sine <= "00111111000111000011110110100100"; cosine <= "10111111010010101100101011100110"; when "0110010110" => sine <= "00111111000110101111111001010101"; cosine <= "10111111010010111011111101010111"; when "0110010111" => sine <= "00111111000110011011110110001000"; cosine <= "10111111010011001011000111010101"; when "0110011000" => sine <= "00111111000110000111101100111111"; cosine <= "10111111010011011010001001011001"; when "0110011001" => sine <= "00111111000101110011011101111110"; cosine <= "10111111010011101001000011100010"; when "0110011010" => sine <= "00111111000101011111001001001000"; cosine <= "10111111010011110111110101101101"; when "0110011011" => sine <= "00111111000101001010101110100000"; cosine <= "10111111010100000110011111110110"; when "0110011100" => sine <= "00111111000100110110001110001010"; cosine <= "10111111010100010101000001111111"; when "0110011101" => sine <= "00111111000100100001101000000111"; cosine <= "10111111010100100011011100000011"; when "0110011110" => sine <= "00111111000100001100111100011100"; cosine <= "10111111010100110001101110000001"; when "0110011111" => sine <= "00111111000011111000001011001100"; cosine <= "10111111010100111111110111110110"; when "0110100000" => sine <= "00111111000011100011010100011001"; cosine <= "10111111010101001101111001011101"; when "0110100001" => sine <= "00111111000011001110011000001000"; cosine <= "10111111010101011011110010111010"; when "0110100010" => sine <= "00111111000010111001010110011011"; cosine <= "10111111010101101001100100000111"; when "0110100011" => sine <= "00111111000010100100001111010101"; cosine <= "10111111010101110111001101000010"; when "0110100100" => sine <= "00111111000010001111000010111010"; cosine <= "10111111010110000100101101101010"; when "0110100101" => sine <= "00111111000001111001110001001110"; cosine <= "10111111010110010010000101111010"; when "0110100110" => sine <= "00111111000001100100011010010011"; cosine <= "10111111010110011111010101110100"; when "0110100111" => sine <= "00111111000001001110111110001100"; cosine <= "10111111010110101100011101010100"; when "0110101000" => sine <= "00111111000000111001011100111110"; cosine <= "10111111010110111001011100011001"; when "0110101001" => sine <= "00111111000000100011110110101010"; cosine <= "10111111010111000110010011000000"; when "0110101010" => sine <= "00111111000000001110001011010110"; cosine <= "10111111010111010011000001000111"; when "0110101011" => sine <= "00111110111111110000110110000110"; cosine <= "10111111010111011111100110101010"; when "0110101100" => sine <= "00111110111111000101001011101011"; cosine <= "10111111010111101100000011101011"; when "0110101101" => sine <= "00111110111110011001010111100010"; cosine <= "10111111010111111000011000000111"; when "0110101110" => sine <= "00111110111101101101011001110000"; cosine <= "10111111011000000100100011111011"; when "0110101111" => sine <= "00111110111101000001010010011110"; cosine <= "10111111011000010000100111000110"; when "0110110000" => sine <= "00111110111100010101000001110001"; cosine <= "10111111011000011100100001100011"; when "0110110001" => sine <= "00111110111011101000100111110001"; cosine <= "10111111011000101000010011010101"; when "0110110010" => sine <= "00111110111010111100000100100101"; cosine <= "10111111011000110011111100011001"; when "0110110011" => sine <= "00111110111010001111011000010010"; cosine <= "10111111011000111111011100101011"; when "0110110100" => sine <= "00111110111001100010100011000001"; cosine <= "10111111011001001010110100001011"; when "0110110101" => sine <= "00111110111000110101100100111000"; cosine <= "10111111011001010110000010110101"; when "0110110110" => sine <= "00111110111000001000011101111110"; cosine <= "10111111011001100001001000101011"; when "0110110111" => sine <= "00111110110111011011001110011001"; cosine <= "10111111011001101100000101101001"; when "0110111000" => sine <= "00111110110110101101110110010010"; cosine <= "10111111011001110110111001101110"; when "0110111001" => sine <= "00111110110110000000010101101111"; cosine <= "10111111011010000001100100110111"; when "0110111010" => sine <= "00111110110101010010101100110110"; cosine <= "10111111011010001100000111000010"; when "0110111011" => sine <= "00111110110100100100111011110000"; cosine <= "10111111011010010110100000010001"; when "0110111100" => sine <= "00111110110011110111000010100010"; cosine <= "10111111011010100000110000011111"; when "0110111101" => sine <= "00111110110011001001000001010101"; cosine <= "10111111011010101010110111101100"; when "0110111110" => sine <= "00111110110010011010111000001111"; cosine <= "10111111011010110100110101110110"; when "0110111111" => sine <= "00111110110001101100100111011000"; cosine <= "10111111011010111110101010111010"; when "0111000000" => sine <= "00111110110000111110001110110101"; cosine <= "10111111011011001000010110111001"; when "0111000001" => sine <= "00111110110000001111101110110000"; cosine <= "10111111011011010001111001110001"; when "0111000010" => sine <= "00111110101111100001000111001110"; cosine <= "10111111011011011011010011011111"; when "0111000011" => sine <= "00111110101110110010011000010111"; cosine <= "10111111011011100100100100000011"; when "0111000100" => sine <= "00111110101110000011100010010011"; cosine <= "10111111011011101101101011011001"; when "0111000101" => sine <= "00111110101101010100100101001000"; cosine <= "10111111011011110110101001100100"; when "0111000110" => sine <= "00111110101100100101100000111101"; cosine <= "10111111011011111111011110011111"; when "0111000111" => sine <= "00111110101011110110010101111011"; cosine <= "10111111011100001000001010001011"; when "0111001000" => sine <= "00111110101011000111000100000111"; cosine <= "10111111011100010000101100100101"; when "0111001001" => sine <= "00111110101010010111101011101010"; cosine <= "10111111011100011001000101101100"; when "0111001010" => sine <= "00111110101001101000001100101011"; cosine <= "10111111011100100001010101011110"; when "0111001011" => sine <= "00111110101000111000100111010001"; cosine <= "10111111011100101001011011111100"; when "0111001100" => sine <= "00111110101000001000111011100100"; cosine <= "10111111011100110001011001000011"; when "0111001101" => sine <= "00111110100111011001001001101010"; cosine <= "10111111011100111001001100110010"; when "0111001110" => sine <= "00111110100110101001010001101100"; cosine <= "10111111011101000000110111001001"; when "0111001111" => sine <= "00111110100101111001010011110000"; cosine <= "10111111011101001000011000000100"; when "0111010000" => sine <= "00111110100101001001001111111110"; cosine <= "10111111011101001111101111100100"; when "0111010001" => sine <= "00111110100100011001000110011101"; cosine <= "10111111011101010110111101101000"; when "0111010010" => sine <= "00111110100011101000110111010101"; cosine <= "10111111011101011110000010001111"; when "0111010011" => sine <= "00111110100010111000100010101110"; cosine <= "10111111011101100100111101010111"; when "0111010100" => sine <= "00111110100010001000001000101110"; cosine <= "10111111011101101011101110111110"; when "0111010101" => sine <= "00111110100001010111101001011101"; cosine <= "10111111011101110010010111000101"; when "0111010110" => sine <= "00111110100000100111000101000011"; cosine <= "10111111011101111000110101101010"; when "0111010111" => sine <= "00111110011111101100110111001110"; cosine <= "10111111011101111111001010101101"; when "0111011000" => sine <= "00111110011110001011011010100010"; cosine <= "10111111011110000101010110001100"; when "0111011001" => sine <= "00111110011100101001110100001111"; cosine <= "10111111011110001011011000000100"; when "0111011010" => sine <= "00111110011011001000000100100110"; cosine <= "10111111011110010001010000011001"; when "0111011011" => sine <= "00111110011001100110001011110110"; cosine <= "10111111011110010110111111000110"; when "0111011100" => sine <= "00111110011000000100001010001101"; cosine <= "10111111011110011100100100001100"; when "0111011101" => sine <= "00111110010110100001111111111010"; cosine <= "10111111011110100001111111101010"; when "0111011110" => sine <= "00111110010100111111101101001101"; cosine <= "10111111011110100111010001011110"; when "0111011111" => sine <= "00111110010011011101010010010110"; cosine <= "10111111011110101100011001101000"; when "0111100000" => sine <= "00111110010001111010101111100010"; cosine <= "10111111011110110001011000001000"; when "0111100001" => sine <= "00111110010000011000000101000010"; cosine <= "10111111011110110110001100111100"; when "0111100010" => sine <= "00111110001110110101010011000100"; cosine <= "10111111011110111010111000000100"; when "0111100011" => sine <= "00111110001101010010011001111000"; cosine <= "10111111011110111111011001011110"; when "0111100100" => sine <= "00111110001011101111011001101100"; cosine <= "10111111011111000011110001001011"; when "0111100101" => sine <= "00111110001010001100010010110010"; cosine <= "10111111011111000111111111001001"; when "0111100110" => sine <= "00111110001000101001000101010110"; cosine <= "10111111011111001100000011011001"; when "0111100111" => sine <= "00111110000111000101110001101010"; cosine <= "10111111011111001111111101111001"; when "0111101000" => sine <= "00111110000101100010010111111100"; cosine <= "10111111011111010011101110101000"; when "0111101001" => sine <= "00111110000011111110111000011011"; cosine <= "10111111011111010111010101100110"; when "0111101010" => sine <= "00111110000010011011010011010111"; cosine <= "10111111011111011010110010110011"; when "0111101011" => sine <= "00111110000000110111101000111111"; cosine <= "10111111011111011110000110001111"; when "0111101100" => sine <= "00111101111110100111110011000110"; cosine <= "10111111011111100001001111110111"; when "0111101101" => sine <= "00111101111011100000001010100011"; cosine <= "10111111011111100100001111101101"; when "0111101110" => sine <= "00111101111000011000011000110110"; cosine <= "10111111011111100111000101101111"; when "0111101111" => sine <= "00111101110101010000011110011011"; cosine <= "10111111011111101001110001111110"; when "0111110000" => sine <= "00111101110010001000011011110011"; cosine <= "10111111011111101100010100011000"; when "0111110001" => sine <= "00111101101111000000010001011101"; cosine <= "10111111011111101110101100111110"; when "0111110010" => sine <= "00111101101011110111111111110110"; cosine <= "10111111011111110000111011101110"; when "0111110011" => sine <= "00111101101000101111100111011110"; cosine <= "10111111011111110011000000101001"; when "0111110100" => sine <= "00111101100101100111001000110101"; cosine <= "10111111011111110100111011101111"; when "0111110101" => sine <= "00111101100010011110100100010111"; cosine <= "10111111011111110110101100111110"; when "0111110110" => sine <= "00111101011110101011110101001100"; cosine <= "10111111011111111000010100010111"; when "0111110111" => sine <= "00111101011000011010010111111111"; cosine <= "10111111011111111001110001111010"; when "0111111000" => sine <= "00111101010010001000110010000100"; cosine <= "10111111011111111011000101100110"; when "0111111001" => sine <= "00111101001011110111000100011011"; cosine <= "10111111011111111100001111011011"; when "0111111010" => sine <= "00111101000101100101010000000001"; cosine <= "10111111011111111101001111011001"; when "0111111011" => sine <= "00111100111110100110101011101000"; cosine <= "10111111011111111110000101100000"; when "0111111100" => sine <= "00111100110010000010101101100100"; cosine <= "10111111011111111110110001101111"; when "0111111101" => sine <= "00111100100101011110100111110010"; cosine <= "10111111011111111111010100000110"; when "0111111110" => sine <= "00111100010001110100111000011100"; cosine <= "10111111011111111111101100100111"; when "0111111111" => sine <= "00111011110001011000110011010010"; cosine <= "10111111011111111111111011001111"; when "1000000000" => sine <= "10111000111000010001111100101010"; cosine <= "10111111100000000000000000000000"; when "1000000001" => sine <= "10111011110011001001010111000010"; cosine <= "10111111011111111111111010111001"; when "1000000010" => sine <= "10111100010010101101001010001000"; cosine <= "10111111011111111111101011111010"; when "1000000011" => sine <= "10111100100101111010110000011101"; cosine <= "10111111011111111111010011000100"; when "1000000100" => sine <= "10111100110010011110110110000000"; cosine <= "10111111011111111110110000010110"; when "1000000101" => sine <= "10111100111111000010110011110000"; cosine <= "10111111011111111110000011110001"; when "1000000110" => sine <= "10111101000101110011010011111001"; cosine <= "10111111011111111101001101010100"; when "1000000111" => sine <= "10111101001100000101001000000101"; cosine <= "10111111011111111100001101000000"; when "1000001000" => sine <= "10111101010010010110110101011110"; cosine <= "10111111011111111011000010110101"; when "1000001001" => sine <= "10111101011000101000011011000110"; cosine <= "10111111011111111001101110110011"; when "1000001010" => sine <= "10111101011110111001110111111111"; cosine <= "10111111011111111000010000111010"; when "1000001011" => sine <= "10111101100010100101100101100101"; cosine <= "10111111011111110110101001001011"; when "1000001100" => sine <= "10111101100101101110001001110110"; cosine <= "10111111011111110100110111100110"; when "1000001101" => sine <= "10111101101000110110101000010010"; cosine <= "10111111011111110010111100001010"; when "1000001110" => sine <= "10111101101011111111000000011011"; cosine <= "10111111011111110000110110111001"; when "1000001111" => sine <= "10111101101111000111010001110010"; cosine <= "10111111011111101110100111110011"; when "1000010000" => sine <= "10111101110010001111011011111000"; cosine <= "10111111011111101100001110110111"; when "1000010001" => sine <= "10111101110101010111011110001110"; cosine <= "10111111011111101001101100000111"; when "1000010010" => sine <= "10111101111000011111011000010110"; cosine <= "10111111011111100110111111100011"; when "1000010011" => sine <= "10111101111011100111001001101111"; cosine <= "10111111011111100100001001001010"; when "1000010100" => sine <= "10111101111110101110110001111101"; cosine <= "10111111011111100001001000111110"; when "1000010101" => sine <= "10111110000000111011001000001111"; cosine <= "10111111011111011101111111000000"; when "1000010110" => sine <= "10111110000010011110110010011011"; cosine <= "10111111011111011010101011001110"; when "1000010111" => sine <= "10111110000100000010010111010011"; cosine <= "10111111011111010111001101101100"; when "1000011000" => sine <= "10111110000101100101110110100111"; cosine <= "10111111011111010011100110010111"; when "1000011001" => sine <= "10111110000111001001010000001000"; cosine <= "10111111011111001111110101010010"; when "1000011010" => sine <= "10111110001000101100100011100111"; cosine <= "10111111011111001011111010011100"; when "1000011011" => sine <= "10111110001010001111110000110100"; cosine <= "10111111011111000111110101110111"; when "1000011100" => sine <= "10111110001011110010110111100000"; cosine <= "10111111011111000011100111100011"; when "1000011101" => sine <= "10111110001101010101110111011100"; cosine <= "10111111011110111111001111100001"; when "1000011110" => sine <= "10111110001110111000110000011000"; cosine <= "10111111011110111010101101110000"; when "1000011111" => sine <= "10111110010000011011100010000101"; cosine <= "10111111011110110110000010010011"; when "1000100000" => sine <= "10111110010001111110001100010101"; cosine <= "10111111011110110001001101001001"; when "1000100001" => sine <= "10111110010011100000101110110111"; cosine <= "10111111011110101100001110010100"; when "1000100010" => sine <= "10111110010101000011001001011101"; cosine <= "10111111011110100111000101110100"; when "1000100011" => sine <= "10111110010110100101011011110111"; cosine <= "10111111011110100001110011101010"; when "1000100100" => sine <= "10111110011000000111100101110110"; cosine <= "10111111011110011100010111110111"; when "1000100101" => sine <= "10111110011001101001100111001100"; cosine <= "10111111011110010110110010011011"; when "1000100110" => sine <= "10111110011011001011011111101000"; cosine <= "10111111011110010001000011011000"; when "1000100111" => sine <= "10111110011100101101001110111101"; cosine <= "10111111011110001011001010101111"; when "1000101000" => sine <= "10111110011110001110110100111010"; cosine <= "10111111011110000101001000100000"; when "1000101001" => sine <= "10111110011111110000010001010001"; cosine <= "10111111011101111110111100101100"; when "1000101010" => sine <= "10111110100000101000110001111001"; cosine <= "10111111011101111000100111010100"; when "1000101011" => sine <= "10111110100001011001010110001000"; cosine <= "10111111011101110010001000011001"; when "1000101100" => sine <= "10111110100010001001110101001101"; cosine <= "10111111011101101011011111111110"; when "1000101101" => sine <= "10111110100010111010001111000001"; cosine <= "10111111011101100100101110000001"; when "1000101110" => sine <= "10111110100011101010100011011100"; cosine <= "10111111011101011101110010100011"; when "1000101111" => sine <= "10111110100100011010110010010111"; cosine <= "10111111011101010110101101101000"; when "1000110000" => sine <= "10111110100101001010111011101011"; cosine <= "10111111011101001111011111001110"; when "1000110001" => sine <= "10111110100101111010111111010000"; cosine <= "10111111011101001000000111011010"; when "1000110010" => sine <= "10111110100110101010111100111111"; cosine <= "10111111011101000000100110001000"; when "1000110011" => sine <= "10111110100111011010110100110000"; cosine <= "10111111011100111000111011011101"; when "1000110100" => sine <= "10111110101000001010100110011100"; cosine <= "10111111011100110001000111011001"; when "1000110101" => sine <= "10111110101000111010010001111100"; cosine <= "10111111011100101001001001111101"; when "1000110110" => sine <= "10111110101001101001110111000111"; cosine <= "10111111011100100001000011001011"; when "1000110111" => sine <= "10111110101010011001010101111000"; cosine <= "10111111011100011000110011000011"; when "1000111000" => sine <= "10111110101011001000101110000110"; cosine <= "10111111011100010000011001100111"; when "1000111001" => sine <= "10111110101011110111111111101010"; cosine <= "10111111011100000111110110111000"; when "1000111010" => sine <= "10111110101100100111001010011110"; cosine <= "10111111011011111111001010111000"; when "1000111011" => sine <= "10111110101101010110001110011000"; cosine <= "10111111011011110110010101101001"; when "1000111100" => sine <= "10111110101110000101001011010100"; cosine <= "10111111011011101101010111001010"; when "1000111101" => sine <= "10111110101110110100000001001000"; cosine <= "10111111011011100100001111011101"; when "1000111110" => sine <= "10111110101111100010101111101111"; cosine <= "10111111011011011010111110100101"; when "1000111111" => sine <= "10111110110000010001010111000000"; cosine <= "10111111011011010001100100100010"; when "1001000000" => sine <= "10111110110000111111110110110101"; cosine <= "10111111011011001000000001011000"; when "1001000001" => sine <= "10111110110001101110001111000110"; cosine <= "10111111011010111110010101000100"; when "1001000010" => sine <= "10111110110010011100011111101100"; cosine <= "10111111011010110100011111101011"; when "1001000011" => sine <= "10111110110011001010101000100001"; cosine <= "10111111011010101010100001001100"; when "1001000100" => sine <= "10111110110011111000101001011100"; cosine <= "10111111011010100000011001101011"; when "1001000101" => sine <= "10111110110100100110100010011000"; cosine <= "10111111011010010110001001001000"; when "1001000110" => sine <= "10111110110101010100010011001100"; cosine <= "10111111011010001011101111101000"; when "1001000111" => sine <= "10111110110110000001111011110010"; cosine <= "10111111011010000001001101000111"; when "1001001000" => sine <= "10111110110110101111011100000010"; cosine <= "10111111011001110110100001101001"; when "1001001001" => sine <= "10111110110111011100110011110110"; cosine <= "10111111011001101011101101010001"; when "1001001010" => sine <= "10111110111000001010000011000111"; cosine <= "10111111011001100000101111111111"; when "1001001011" => sine <= "10111110111000110111001001101110"; cosine <= "10111111011001010101101001110111"; when "1001001100" => sine <= "10111110111001100100000111100100"; cosine <= "10111111011001001010011010110111"; when "1001001101" => sine <= "10111110111010010000111100100001"; cosine <= "10111111011000111111000011000100"; when "1001001110" => sine <= "10111110111010111101101000011111"; cosine <= "10111111011000110011100010011101"; when "1001001111" => sine <= "10111110111011101010001011010111"; cosine <= "10111111011000100111111001000110"; when "1001010000" => sine <= "10111110111100010110100101000011"; cosine <= "10111111011000011100000111000011"; when "1001010001" => sine <= "10111110111101000010110101011010"; cosine <= "10111111011000010000001100010000"; when "1001010010" => sine <= "10111110111101101110111100010111"; cosine <= "10111111011000000100001000110010"; when "1001010011" => sine <= "10111110111110011010111001110011"; cosine <= "10111111010111110111111100101010"; when "1001010100" => sine <= "10111110111111000110101101100111"; cosine <= "10111111010111101011100111111011"; when "1001010101" => sine <= "10111110111111110010010111101100"; cosine <= "10111111010111011111001010101001"; when "1001010110" => sine <= "10111111000000001110111011111110"; cosine <= "10111111010111010010100100110000"; when "1001010111" => sine <= "10111111000000100100100111000111"; cosine <= "10111111010111000101110110010110"; when "1001011000" => sine <= "10111111000000111010001101001111"; cosine <= "10111111010110111000111111011101"; when "1001011001" => sine <= "10111111000001001111101110010010"; cosine <= "10111111010110101100000000000101"; when "1001011010" => sine <= "10111111000001100101001010001101"; cosine <= "10111111010110011110111000010100"; when "1001011011" => sine <= "10111111000001111010100000111101"; cosine <= "10111111010110010001101000000111"; when "1001011100" => sine <= "10111111000010001111110010011110"; cosine <= "10111111010110000100001111100010"; when "1001011101" => sine <= "10111111000010100100111110101100"; cosine <= "10111111010101110110101110101000"; when "1001011110" => sine <= "10111111000010111010000101100110"; cosine <= "10111111010101101001000101011010"; when "1001011111" => sine <= "10111111000011001111000111000111"; cosine <= "10111111010101011011010011111100"; when "1001100000" => sine <= "10111111000011100100000011001100"; cosine <= "10111111010101001101011010001110"; when "1001100001" => sine <= "10111111000011111000111001110010"; cosine <= "10111111010100111111011000010010"; when "1001100010" => sine <= "10111111000100001101101010110110"; cosine <= "10111111010100110001001110001011"; when "1001100011" => sine <= "10111111000100100010010110010101"; cosine <= "10111111010100100010111011111011"; when "1001100100" => sine <= "10111111000100110110111100001010"; cosine <= "10111111010100010100100001100100"; when "1001100101" => sine <= "10111111000101001011011100010100"; cosine <= "10111111010100000101111111001100"; when "1001100110" => sine <= "10111111000101011111110110101111"; cosine <= "10111111010011110111010100101110"; when "1001100111" => sine <= "10111111000101110100001011011000"; cosine <= "10111111010011101000100010010001"; when "1001101000" => sine <= "10111111000110001000011010001100"; cosine <= "10111111010011011001100111110111"; when "1001101001" => sine <= "10111111000110011100100011001000"; cosine <= "10111111010011001010100101100001"; when "1001101010" => sine <= "10111111000110110000100110000111"; cosine <= "10111111010010111011011011010100"; when "1001101011" => sine <= "10111111000111000100100011001001"; cosine <= "10111111010010101100001001001110"; when "1001101100" => sine <= "10111111000111011000011010001000"; cosine <= "10111111010010011100101111010100"; when "1001101101" => sine <= "10111111000111101100001011000011"; cosine <= "10111111010010001101001101101000"; when "1001101110" => sine <= "10111111000111111111110101110111"; cosine <= "10111111010001111101100100001101"; when "1001101111" => sine <= "10111111001000010011011010011111"; cosine <= "10111111010001101101110011000111"; when "1001110000" => sine <= "10111111001000100110111000111010"; cosine <= "10111111010001011101111010010011"; when "1001110001" => sine <= "10111111001000111010010001000100"; cosine <= "10111111010001001101111001111000"; when "1001110010" => sine <= "10111111001001001101100010111010"; cosine <= "10111111010000111101110001110110"; when "1001110011" => sine <= "10111111001001100000101110011001"; cosine <= "10111111010000101101100010010001"; when "1001110100" => sine <= "10111111001001110011110011011110"; cosine <= "10111111010000011101001011001110"; when "1001110101" => sine <= "10111111001010000110110010000111"; cosine <= "10111111010000001100101100101011"; when "1001110110" => sine <= "10111111001010011001101010010001"; cosine <= "10111111001111111100000110101011"; when "1001110111" => sine <= "10111111001010101100011011110111"; cosine <= "10111111001111101011011001010010"; when "1001111000" => sine <= "10111111001010111111000110111001"; cosine <= "10111111001111011010100100100011"; when "1001111001" => sine <= "10111111001011010001101011010010"; cosine <= "10111111001111001001101000100010"; when "1001111010" => sine <= "10111111001011100100001001000000"; cosine <= "10111111001110111000100101001110"; when "1001111011" => sine <= "10111111001011110110100000000000"; cosine <= "10111111001110100111011010101010"; when "1001111100" => sine <= "10111111001100001000110000001111"; cosine <= "10111111001110010110001000111011"; when "1001111101" => sine <= "10111111001100011010111001101010"; cosine <= "10111111001110000100110000000010"; when "1001111110" => sine <= "10111111001100101100111100001111"; cosine <= "10111111001101110011010000000101"; when "1001111111" => sine <= "10111111001100111110110111111011"; cosine <= "10111111001101100001101001000001"; when "1010000000" => sine <= "10111111001101010000101100101011"; cosine <= "10111111001101001111111010111100"; when "1010000001" => sine <= "10111111001101100010011010011100"; cosine <= "10111111001100111110000101111000"; when "1010000010" => sine <= "10111111001101110100000001001100"; cosine <= "10111111001100101100001001111000"; when "1010000011" => sine <= "10111111001110000101100000110111"; cosine <= "10111111001100011010000110111111"; when "1010000100" => sine <= "10111111001110010110111001011100"; cosine <= "10111111001100000111111101010011"; when "1010000101" => sine <= "10111111001110101000001010110111"; cosine <= "10111111001011110101101100110000"; when "1010000110" => sine <= "10111111001110111001010101000101"; cosine <= "10111111001011100011010101011101"; when "1010000111" => sine <= "10111111001111001010011000000101"; cosine <= "10111111001011010000110111011100"; when "1010001000" => sine <= "10111111001111011011010011110100"; cosine <= "10111111001010111110010010101111"; when "1010001001" => sine <= "10111111001111101100001000001110"; cosine <= "10111111001010101011100111011110"; when "1010001010" => sine <= "10111111001111111100110101010010"; cosine <= "10111111001010011000110101100100"; when "1010001011" => sine <= "10111111010000001101011010111100"; cosine <= "10111111001010000101111101001000"; when "1010001100" => sine <= "10111111010000011101111001001010"; cosine <= "10111111001001110010111110001100"; when "1010001101" => sine <= "10111111010000101110001111111010"; cosine <= "10111111001001011111111000110111"; when "1010001110" => sine <= "10111111010000111110011111001001"; cosine <= "10111111001001001100101101000011"; when "1010001111" => sine <= "10111111010001001110100110110101"; cosine <= "10111111001000111001011010111101"; when "1010010000" => sine <= "10111111010001011110100110111011"; cosine <= "10111111001000100110000010100100"; when "1010010001" => sine <= "10111111010001101110011111011001"; cosine <= "10111111001000010010100011110101"; when "1010010010" => sine <= "10111111010001111110010000001011"; cosine <= "10111111000111111110111110111101"; when "1010010011" => sine <= "10111111010010001101111001010001"; cosine <= "10111111000111101011010011110101"; when "1010010100" => sine <= "10111111010010011101011010100110"; cosine <= "10111111000111010111100010101100"; when "1010010101" => sine <= "10111111010010101100110100001010"; cosine <= "10111111000111000011101011010111"; when "1010010110" => sine <= "10111111010010111100000101111010"; cosine <= "10111111000110101111101110001000"; when "1010010111" => sine <= "10111111010011001011001111110010"; cosine <= "10111111000110011011101010111010"; when "1010011000" => sine <= "10111111010011011010010001110001"; cosine <= "10111111000110000111100001101010"; when "1010011001" => sine <= "10111111010011101001001011110101"; cosine <= "10111111000101110011010010101001"; when "1010011010" => sine <= "10111111010011110111111101111100"; cosine <= "10111111000101011110111101101011"; when "1010011011" => sine <= "10111111010100000110101000000010"; cosine <= "10111111000101001010100011000011"; when "1010011100" => sine <= "10111111010100010101001010000110"; cosine <= "10111111000100110110000010101011"; when "1010011101" => sine <= "10111111010100100011100100000101"; cosine <= "10111111000100100001011100100010"; when "1010011110" => sine <= "10111111010100110001110101111110"; cosine <= "10111111000100001100110000110110"; when "1010011111" => sine <= "10111111010100111111111111101110"; cosine <= "10111111000011110111111111011111"; when "1010100000" => sine <= "10111111010101001110000001010010"; cosine <= "10111111000011100011001000101100"; when "1010100001" => sine <= "10111111010101011011111010101010"; cosine <= "10111111000011001110001100011010"; when "1010100010" => sine <= "10111111010101101001101011110010"; cosine <= "10111111000010111001001010100110"; when "1010100011" => sine <= "10111111010101110111010100101000"; cosine <= "10111111000010100100000011100000"; when "1010100100" => sine <= "10111111010110000100110101001011"; cosine <= "10111111000010001110110110111111"; when "1010100101" => sine <= "10111111010110010010001101011000"; cosine <= "10111111000001111001100101010010"; when "1010100110" => sine <= "10111111010110011111011101001101"; cosine <= "10111111000001100100001110010110"; when "1010100111" => sine <= "10111111010110101100100100101000"; cosine <= "10111111000001001110110010001001"; when "1010101000" => sine <= "10111111010110111001100011101000"; cosine <= "10111111000000111001010000111010"; when "1010101001" => sine <= "10111111010111000110011010001001"; cosine <= "10111111000000100011101010100000"; when "1010101010" => sine <= "10111111010111010011001000001011"; cosine <= "10111111000000001101111111001011"; when "1010101011" => sine <= "10111111010111011111101101101011"; cosine <= "10111110111111110000011101110001"; when "1010101100" => sine <= "10111111010111101100001010100111"; cosine <= "10111110111111000100110011001001"; when "1010101101" => sine <= "10111111010111111000011110111110"; cosine <= "10111110111110011000111111000000"; when "1010101110" => sine <= "10111111011000000100101010101101"; cosine <= "10111110111101101101000001000001"; when "1010101111" => sine <= "10111111011000010000101101110010"; cosine <= "10111110111101000000111001101111"; when "1010110000" => sine <= "10111111011000011100101000001100"; cosine <= "10111110111100010100101001000011"; when "1010110001" => sine <= "10111111011000101000011001111001"; cosine <= "10111110111011101000001110110101"; when "1010110010" => sine <= "10111111011000110100000010110111"; cosine <= "10111110111010111011101011101001"; when "1010110011" => sine <= "10111111011000111111100011000101"; cosine <= "10111110111010001110111111001001"; when "1010110100" => sine <= "10111111011001001010111010011111"; cosine <= "10111110111001100010001001111000"; when "1010110101" => sine <= "10111111011001010110001001000110"; cosine <= "10111110111000110101001011110000"; when "1010110110" => sine <= "10111111011001100001001110110110"; cosine <= "10111110111000001000000100101000"; when "1010110111" => sine <= "10111111011001101100001011101111"; cosine <= "10111110110111011010110101000101"; when "1010111000" => sine <= "10111111011001110110111111101110"; cosine <= "10111110110110101101011100110000"; when "1010111001" => sine <= "10111111011010000001101010110010"; cosine <= "10111110110101111111111100001110"; when "1010111010" => sine <= "10111111011010001100001100111010"; cosine <= "10111110110101010010010011010111"; when "1010111011" => sine <= "10111111011010010110100110000011"; cosine <= "10111110110100100100100010000011"; when "1010111100" => sine <= "10111111011010100000110110001100"; cosine <= "10111110110011110110101000110111"; when "1010111101" => sine <= "10111111011010101010111101010100"; cosine <= "10111110110011001000100111011101"; when "1010111110" => sine <= "10111111011010110100111011011000"; cosine <= "10111110110010011010011110011001"; when "1010111111" => sine <= "10111111011010111110110000011000"; cosine <= "10111110110001101100001101100010"; when "1011000000" => sine <= "10111111011011001000011100010010"; cosine <= "10111110110000111101110100110011"; when "1011000001" => sine <= "10111111011011010001111111000100"; cosine <= "10111110110000001111010100101111"; when "1011000010" => sine <= "10111111011011011011011000101101"; cosine <= "10111110101111100000101101000001"; when "1011000011" => sine <= "10111111011011100100101001001011"; cosine <= "10111110101110110001111110001100"; when "1011000100" => sine <= "10111111011011101101110000011110"; cosine <= "10111110101110000011001000001001"; when "1011000101" => sine <= "10111111011011110110101110100011"; cosine <= "10111110101101010100001010110001"; when "1011000110" => sine <= "10111111011011111111100011011001"; cosine <= "10111110101100100101000110101001"; when "1011000111" => sine <= "10111111011100001000001110111111"; cosine <= "10111110101011110101111011011010"; when "1011001000" => sine <= "10111111011100010000110001010100"; cosine <= "10111110101011000110101001101001"; when "1011001001" => sine <= "10111111011100011001001010010110"; cosine <= "10111110101010010111010001001110"; when "1011001010" => sine <= "10111111011100100001011010000011"; cosine <= "10111110101001100111110010000010"; when "1011001011" => sine <= "10111111011100101001100000011100"; cosine <= "10111110101000111000001100101011"; when "1011001100" => sine <= "10111111011100110001011101011101"; cosine <= "10111110101000001000100000110001"; when "1011001101" => sine <= "10111111011100111001010001000111"; cosine <= "10111110100111011000101110111010"; when "1011001110" => sine <= "10111111011101000000111011011000"; cosine <= "10111110100110101000110110111110"; when "1011001111" => sine <= "10111111011101001000011100001111"; cosine <= "10111110100101111000111000110110"; when "1011010000" => sine <= "10111111011101001111110011101010"; cosine <= "10111110100101001000110101000111"; when "1011010001" => sine <= "10111111011101010111000001101000"; cosine <= "10111110100100011000101011011010"; when "1011010010" => sine <= "10111111011101011110000110001001"; cosine <= "10111110100011101000011100010101"; when "1011010011" => sine <= "10111111011101100101000001001100"; cosine <= "10111110100010111000000111100001"; when "1011010100" => sine <= "10111111011101101011110010101110"; cosine <= "10111110100010000111101101100101"; when "1011010101" => sine <= "10111111011101110010011010110000"; cosine <= "10111110100001010111001110010111"; when "1011010110" => sine <= "10111111011101111000111001010000"; cosine <= "10111110100000100110101001110001"; when "1011010111" => sine <= "10111111011101111111001110001101"; cosine <= "10111110011111101100000000110010"; when "1011011000" => sine <= "10111111011110000101011001100110"; cosine <= "10111110011110001010100011101101"; when "1011011001" => sine <= "10111111011110001011011011011010"; cosine <= "10111110011100101000111101100010"; when "1011011010" => sine <= "10111111011110010001010011101001"; cosine <= "10111110011011000111001110000000"; when "1011011011" => sine <= "10111111011110010111000010010001"; cosine <= "10111110011001100101010100111000"; when "1011011100" => sine <= "10111111011110011100100111010001"; cosine <= "10111110011000000011010011010111"; when "1011011101" => sine <= "10111111011110100010000010101001"; cosine <= "10111110010110100001001000101101"; when "1011011110" => sine <= "10111111011110100111010100011000"; cosine <= "10111110010100111110110110001000"; when "1011011111" => sine <= "10111111011110101100011100011101"; cosine <= "10111110010011011100011011011000"; when "1011100000" => sine <= "10111111011110110001011010110111"; cosine <= "10111110010001111001111000001101"; when "1011100001" => sine <= "10111111011110110110001111100110"; cosine <= "10111110010000010111001101110101"; when "1011100010" => sine <= "10111111011110111010111010101000"; cosine <= "10111110001110110100011011100001"; when "1011100011" => sine <= "10111111011110111111011011111101"; cosine <= "10111110001101010001100010011101"; when "1011100100" => sine <= "10111111011111000011110011100101"; cosine <= "10111110001011101110100010011011"; when "1011100101" => sine <= "10111111011111001000000001011110"; cosine <= "10111110001010001011011011001010"; when "1011100110" => sine <= "10111111011111001100000101101000"; cosine <= "10111110001000101000001101110111"; when "1011100111" => sine <= "10111111011111010000000000000010"; cosine <= "10111110000111000100111001110101"; when "1011101000" => sine <= "10111111011111010011110000101100"; cosine <= "10111110000101100001100000010000"; when "1011101001" => sine <= "10111111011111010111010111100101"; cosine <= "10111110000011111110000000111001"; when "1011101010" => sine <= "10111111011111011010110100101100"; cosine <= "10111110000010011010011011011111"; when "1011101011" => sine <= "10111111011111011110001000000010"; cosine <= "10111110000000110110110001010001"; when "1011101100" => sine <= "10111111011111100001010001100101"; cosine <= "10111101111110100110000010111110"; when "1011101101" => sine <= "10111111011111100100010001010110"; cosine <= "10111101111011011110011010110000"; when "1011101110" => sine <= "10111111011111100111000111010010"; cosine <= "10111101111000010110101001010111"; when "1011101111" => sine <= "10111111011111101001110011011011"; cosine <= "10111101110101001110101110010010"; when "1011110000" => sine <= "10111111011111101100010101110000"; cosine <= "10111101110010000110101011111111"; when "1011110001" => sine <= "10111111011111101110101110010000"; cosine <= "10111101101110111110100000111110"; when "1011110010" => sine <= "10111111011111110000111100111011"; cosine <= "10111101101011110110001111101110"; when "1011110011" => sine <= "10111111011111110011000001110001"; cosine <= "10111101101000101101110111101100"; when "1011110100" => sine <= "10111111011111110100111100110001"; cosine <= "10111101100101100101011000011001"; when "1011110101" => sine <= "10111111011111110110101101111011"; cosine <= "10111101100010011100110100010010"; when "1011110110" => sine <= "10111111011111111000010101001110"; cosine <= "10111101011110101000010011101111"; when "1011110111" => sine <= "10111111011111111001110010101100"; cosine <= "10111101011000010110110111010000"; when "1011111000" => sine <= "10111111011111111011000110010010"; cosine <= "10111101010010000101010010000101"; when "1011111001" => sine <= "10111111011111111100010000000010"; cosine <= "10111101001011110011100011001011"; when "1011111010" => sine <= "10111111011111111101001111111010"; cosine <= "10111101000101100001101111100001"; when "1011111011" => sine <= "10111111011111111110000101111011"; cosine <= "10111100111110011111101000001010"; when "1011111100" => sine <= "10111111011111111110110010000101"; cosine <= "10111100110001111011101011101000"; when "1011111101" => sine <= "10111111011111111111010100010111"; cosine <= "10111100100101010111100111011010"; when "1011111110" => sine <= "10111111011111111111101100110010"; cosine <= "10111100010001100110110010110101"; when "1011111111" => sine <= "10111111011111111111111011010101"; cosine <= "10111011110000111100101110011010"; when "1100000000" => sine <= "10111111100000000000000000000000"; cosine <= "00111001001010010000001100110011"; when "1100000001" => sine <= "10111111011111111111111010110011"; cosine <= "00111011110011100101011111000000"; when "1100000010" => sine <= "10111111011111111111101011101111"; cosine <= "00111100010010111011001010110101"; when "1100000011" => sine <= "10111111011111111111010010110011"; cosine <= "00111100100110000001110011001001"; when "1100000100" => sine <= "10111111011111111110110000000000"; cosine <= "00111100110010100101110111000001"; when "1100000101" => sine <= "10111111011111111110000011010101"; cosine <= "00111100111111001001110111000101"; when "1100000110" => sine <= "10111111011111111101001100110011"; cosine <= "00111101000101110110110100101101"; when "1100000111" => sine <= "10111111011111111100001100011010"; cosine <= "00111101001100001000101000000010"; when "1100001000" => sine <= "10111111011111111011000010001001"; cosine <= "00111101010010011010010110100011"; when "1100001001" => sine <= "10111111011111111001101110000001"; cosine <= "00111101011000101011111011010011"; when "1100001010" => sine <= "10111111011111111000010000000011"; cosine <= "00111101011110111101011001010011"; when "1100001011" => sine <= "10111111011111110110101000001110"; cosine <= "00111101100010100111010101110011"; when "1100001100" => sine <= "10111111011111110100110110100011"; cosine <= "00111101100101101111111001100111"; when "1100001101" => sine <= "10111111011111110010111011000010"; cosine <= "00111101101000111000011000100110"; when "1100001110" => sine <= "10111111011111110000110101101100"; cosine <= "00111101101100000000110000010001"; when "1100001111" => sine <= "10111111011111101110100110100000"; cosine <= "00111101101111001001000010001010"; when "1100010000" => sine <= "10111111011111101100001101011111"; cosine <= "00111101110010010001001011110010"; when "1100010001" => sine <= "10111111011111101001101010101001"; cosine <= "00111101110101011001001110101010"; when "1100010010" => sine <= "10111111011111100110111101111111"; cosine <= "00111101111000100001001000010011"; when "1100010011" => sine <= "10111111011111100100000111100001"; cosine <= "00111101111011101000111001001110"; when "1100010100" => sine <= "10111111011111100001000111010000"; cosine <= "00111101111110110000100001111100"; when "1100010101" => sine <= "10111111011111011101111101001100"; cosine <= "00111110000000111011111111111111"; when "1100010110" => sine <= "10111111011111011010101001010101"; cosine <= "00111110000010011111101010011100"; when "1100010111" => sine <= "10111111011111010111001011101101"; cosine <= "00111110000100000011001111000100"; when "1100011000" => sine <= "10111111011111010011100100010011"; cosine <= "00111110000101100110101110001000"; when "1100011001" => sine <= "10111111011111001111110011001000"; cosine <= "00111110000111001010000111111000"; when "1100011010" => sine <= "10111111011111001011111000001101"; cosine <= "00111110001000101101011011000111"; when "1100011011" => sine <= "10111111011111000111110011100011"; cosine <= "00111110001010010000101000100011"; when "1100011100" => sine <= "10111111011111000011100101001001"; cosine <= "00111110001011110011101110111111"; when "1100011101" => sine <= "10111111011110111111001101000001"; cosine <= "00111110001101010110101110101010"; when "1100011110" => sine <= "10111111011110111010101011001011"; cosine <= "00111110001110111001100111110101"; when "1100011111" => sine <= "10111111011110110101111111101000"; cosine <= "00111110010000011100011001010001"; when "1100100000" => sine <= "10111111011110110001001010011001"; cosine <= "00111110010001111111000011101111"; when "1100100001" => sine <= "10111111011110101100001011011111"; cosine <= "00111110010011100001100110000000"; when "1100100010" => sine <= "10111111011110100111000010111001"; cosine <= "00111110010101000100000000010101"; when "1100100011" => sine <= "10111111011110100001110000101010"; cosine <= "00111110010110100110010010111101"; when "1100100100" => sine <= "10111111011110011100010100110010"; cosine <= "00111110011000001000011100101011"; when "1100100101" => sine <= "10111111011110010110101111010001"; cosine <= "00111110011001101010011110001110"; when "1100100110" => sine <= "10111111011110010001000000001000"; cosine <= "00111110011011001100010110011001"; when "1100100111" => sine <= "10111111011110001011000111011010"; cosine <= "00111110011100101110000101011100"; when "1100101000" => sine <= "10111111011110000101000101000101"; cosine <= "00111110011110001111101011100110"; when "1100101001" => sine <= "10111111011101111110111001001100"; cosine <= "00111110011111110001000111101011"; when "1100101010" => sine <= "10111111011101111000100011101111"; cosine <= "00111110100000101001001101001101"; when "1100101011" => sine <= "10111111011101110010000100101111"; cosine <= "00111110100001011001110001010010"; when "1100101100" => sine <= "10111111011101101011011100001101"; cosine <= "00111110100010001010010000001110"; when "1100101101" => sine <= "10111111011101100100101010001011"; cosine <= "00111110100010111010101010001001"; when "1100101110" => sine <= "10111111011101011101101110101001"; cosine <= "00111110100011101010111110011011"; when "1100101111" => sine <= "10111111011101010110101001101000"; cosine <= "00111110100100011011001101011100"; when "1100110000" => sine <= "10111111011101001111011011001001"; cosine <= "00111110100101001011010110100111"; when "1100110001" => sine <= "10111111011101001000000011001110"; cosine <= "00111110100101111011011010000010"; when "1100110010" => sine <= "10111111011101000000100001111000"; cosine <= "00111110100110101011010111110111"; when "1100110011" => sine <= "10111111011100111000110111001000"; cosine <= "00111110100111011011001111011110"; when "1100110100" => sine <= "10111111011100110001000010111110"; cosine <= "00111110101000001011000001010000"; when "1100110101" => sine <= "10111111011100101001000101011101"; cosine <= "00111110101000111010101100100110"; when "1100110110" => sine <= "10111111011100100000111110100110"; cosine <= "00111110101001101010010001101000"; when "1100110111" => sine <= "10111111011100011000101110011001"; cosine <= "00111110101010011001110000011110"; when "1100111000" => sine <= "10111111011100010000010100110111"; cosine <= "00111110101011001001001000100010"; when "1100111001" => sine <= "10111111011100000111110010000100"; cosine <= "00111110101011111000011010001100"; when "1100111010" => sine <= "10111111011011111111000101111111"; cosine <= "00111110101100100111100100110101"; when "1100111011" => sine <= "10111111011011110110010000101001"; cosine <= "00111110101101010110101000100110"; when "1100111100" => sine <= "10111111011011101101010010000101"; cosine <= "00111110101110000101100101100110"; when "1100111101" => sine <= "10111111011011100100001010010100"; cosine <= "00111110101110110100011011010001"; when "1100111110" => sine <= "10111111011011011010111001010111"; cosine <= "00111110101111100011001001111100"; when "1100111111" => sine <= "10111111011011010001011111001111"; cosine <= "00111110110000010001110001000011"; when "1101000000" => sine <= "10111111011011000111111011111110"; cosine <= "00111110110001000000010000101110"; when "1101000001" => sine <= "10111111011010111110001111100110"; cosine <= "00111110110001101110101001000100"; when "1101000010" => sine <= "10111111011010110100011010001000"; cosine <= "00111110110010011100111001100000"; when "1101000011" => sine <= "10111111011010101010011011100101"; cosine <= "00111110110011001011000010011000"; when "1101000100" => sine <= "10111111011010100000010011111111"; cosine <= "00111110110011111001000011001010"; when "1101000101" => sine <= "10111111011010010110000011010111"; cosine <= "00111110110100100110111011111010"; when "1101000110" => sine <= "10111111011010001011101001110000"; cosine <= "00111110110101010100101100110011"; when "1101000111" => sine <= "10111111011010000001000111001010"; cosine <= "00111110110110000010010101001110"; when "1101001000" => sine <= "10111111011001110110011011101000"; cosine <= "00111110110110101111110101100011"; when "1101001001" => sine <= "10111111011001101011100111001011"; cosine <= "00111110110111011101001101001100"; when "1101001010" => sine <= "10111111011001100000101001110100"; cosine <= "00111110111000001010011100010011"; when "1101001011" => sine <= "10111111011001010101100011100110"; cosine <= "00111110111000110111100010111101"; when "1101001100" => sine <= "10111111011001001010010100100010"; cosine <= "00111110111001100100100000101000"; when "1101001101" => sine <= "10111111011000111110111100101010"; cosine <= "00111110111010010001010101101001"; when "1101001110" => sine <= "10111111011000110011011011111111"; cosine <= "00111110111010111110000001011100"; when "1101001111" => sine <= "10111111011000100111110010100011"; cosine <= "00111110111011101010100100011000"; when "1101010000" => sine <= "10111111011000011100000000011001"; cosine <= "00111110111100010110111101111000"; when "1101010001" => sine <= "10111111011000010000000101100010"; cosine <= "00111110111101000011001110000101"; when "1101010010" => sine <= "10111111011000000100000001111111"; cosine <= "00111110111101101111010101000101"; when "1101010011" => sine <= "10111111010111110111110101110011"; cosine <= "00111110111110011011010010010110"; when "1101010100" => sine <= "10111111010111101011100001000000"; cosine <= "00111110111111000111000110001100"; when "1101010101" => sine <= "10111111010111011111000011100111"; cosine <= "00111110111111110010110000000110"; when "1101010110" => sine <= "10111111010111010010011101101010"; cosine <= "00111111000000001111001000000101"; when "1101010111" => sine <= "10111111010111000101101111001100"; cosine <= "00111111000000100100110011010000"; when "1101011000" => sine <= "10111111010110111000111000001110"; cosine <= "00111111000000111010011001010010"; when "1101011001" => sine <= "10111111010110101011111000110010"; cosine <= "00111111000001001111111010010111"; when "1101011010" => sine <= "10111111010110011110110000111011"; cosine <= "00111111000001100101010110001100"; when "1101011011" => sine <= "10111111010110010001100000101001"; cosine <= "00111111000001111010101100110110"; when "1101011100" => sine <= "10111111010110000100001000000000"; cosine <= "00111111000010001111111110011000"; when "1101011101" => sine <= "10111111010101110110100111000001"; cosine <= "00111111000010100101001010100001"; when "1101011110" => sine <= "10111111010101101000111101101111"; cosine <= "00111111000010111010010001011100"; when "1101011111" => sine <= "10111111010101011011001100001100"; cosine <= "00111111000011001111010010110111"; when "1101100000" => sine <= "10111111010101001101010010011001"; cosine <= "00111111000011100100001110110110"; when "1101100001" => sine <= "10111111010100111111010000011000"; cosine <= "00111111000011111001000101011101"; when "1101100010" => sine <= "10111111010100110001000110001101"; cosine <= "00111111000100001101110110011011"; when "1101100011" => sine <= "10111111010100100010110011111001"; cosine <= "00111111000100100010100001111011"; when "1101100100" => sine <= "10111111010100010100011001011111"; cosine <= "00111111000100110111000111101011"; when "1101100101" => sine <= "10111111010100000101110111000000"; cosine <= "00111111000101001011100111101111"; when "1101100110" => sine <= "10111111010011110111001100011111"; cosine <= "00111111000101100000000010001011"; when "1101100111" => sine <= "10111111010011101000011001111110"; cosine <= "00111111000101110100010110101110"; when "1101101000" => sine <= "10111111010011011001011111011111"; cosine <= "00111111000110001000100101100010"; when "1101101001" => sine <= "10111111010011001010011101000101"; cosine <= "00111111000110011100101110010111"; when "1101101010" => sine <= "10111111010010111011010010110010"; cosine <= "00111111000110110000110001010001"; when "1101101011" => sine <= "10111111010010101100000000101000"; cosine <= "00111111000111000100101110010011"; when "1101101100" => sine <= "10111111010010011100100110101010"; cosine <= "00111111000111011000100101001101"; when "1101101101" => sine <= "10111111010010001101000100111010"; cosine <= "00111111000111101100010110001000"; when "1101101110" => sine <= "10111111010001111101011011011011"; cosine <= "00111111001000000000000000110110"; when "1101101111" => sine <= "10111111010001101101101010001111"; cosine <= "00111111001000010011100101011000"; when "1101110000" => sine <= "10111111010001011101110001010111"; cosine <= "00111111001000100111000011110011"; when "1101110001" => sine <= "10111111010001001101110000111000"; cosine <= "00111111001000111010011011110111"; when "1101110010" => sine <= "10111111010000111101101000110011"; cosine <= "00111111001001001101101101101101"; when "1101110011" => sine <= "10111111010000101101011001001010"; cosine <= "00111111001001100000111001000110"; when "1101110100" => sine <= "10111111010000011101000010000001"; cosine <= "00111111001001110011111110000110"; when "1101110101" => sine <= "10111111010000001100100011011010"; cosine <= "00111111001010000110111100101110"; when "1101110110" => sine <= "10111111001111111011111101010110"; cosine <= "00111111001010011001110100110010"; when "1101110111" => sine <= "10111111001111101011001111111010"; cosine <= "00111111001010101100100110011000"; when "1101111000" => sine <= "10111111001111011010011011000111"; cosine <= "00111111001010111111010001010100"; when "1101111001" => sine <= "10111111001111001001011111000000"; cosine <= "00111111001011010001110101100111"; when "1101111010" => sine <= "10111111001110111000011011101000"; cosine <= "00111111001011100100010011010100"; when "1101111011" => sine <= "10111111001110100111010001000001"; cosine <= "00111111001011110110101010001110"; when "1101111100" => sine <= "10111111001110010101111111001110"; cosine <= "00111111001100001000111010011101"; when "1101111101" => sine <= "10111111001110000100100110010010"; cosine <= "00111111001100011011000011110010"; when "1101111110" => sine <= "10111111001101110011000110001110"; cosine <= "00111111001100101101000110010001"; when "1101111111" => sine <= "10111111001101100001011111000111"; cosine <= "00111111001100111111000001111100"; when "1110000000" => sine <= "10111111001101001111110000111110"; cosine <= "00111111001101010000110110100110"; when "1110000001" => sine <= "10111111001100111101111011110111"; cosine <= "00111111001101100010100100010111"; when "1110000010" => sine <= "10111111001100101011111111110100"; cosine <= "00111111001101110100001011000000"; when "1110000011" => sine <= "10111111001100011001111100111000"; cosine <= "00111111001110000101101010100101"; when "1110000100" => sine <= "10111111001100000111110011000110"; cosine <= "00111111001110010111000011001001"; when "1110000101" => sine <= "10111111001011110101100010100000"; cosine <= "00111111001110101000010100011110"; when "1110000110" => sine <= "10111111001011100011001011001001"; cosine <= "00111111001110111001011110101100"; when "1110000111" => sine <= "10111111001011010000101101000101"; cosine <= "00111111001111001010100001100110"; when "1110001000" => sine <= "10111111001010111110001000010101"; cosine <= "00111111001111011011011101001110"; when "1110001001" => sine <= "10111111001010101011011100111110"; cosine <= "00111111001111101100010001100111"; when "1110001010" => sine <= "10111111001010011000101011000001"; cosine <= "00111111001111111100111110100100"; when "1110001011" => sine <= "10111111001010000101110010100010"; cosine <= "00111111010000001101100100001110"; when "1110001100" => sine <= "10111111001001110010110011100011"; cosine <= "00111111010000011110000010010110"; when "1110001101" => sine <= "10111111001001011111101110001000"; cosine <= "00111111010000101110011001000101"; when "1110001110" => sine <= "10111111001001001100100010010011"; cosine <= "00111111010000111110101000001110"; when "1110001111" => sine <= "10111111001000111001010000001000"; cosine <= "00111111010001001110101111110011"; when "1110010000" => sine <= "10111111001000100101110111101001"; cosine <= "00111111010001011110101111111000"; when "1110010001" => sine <= "10111111001000010010011000111010"; cosine <= "00111111010001101110101000001111"; when "1110010010" => sine <= "10111111000111111110110011111100"; cosine <= "00111111010001111110011001000000"; when "1110010011" => sine <= "10111111000111101011001000110100"; cosine <= "00111111010010001110000001111111"; when "1110010100" => sine <= "10111111000111010111010111100101"; cosine <= "00111111010010011101100011001111"; when "1110010101" => sine <= "10111111000111000011100000010001"; cosine <= "00111111010010101100111100110001"; when "1110010110" => sine <= "10111111000110101111100010111100"; cosine <= "00111111010010111100001110011010"; when "1110010111" => sine <= "10111111000110011011011111101000"; cosine <= "00111111010011001011011000010001"; when "1110011000" => sine <= "10111111000110000111010110011000"; cosine <= "00111111010011011010011010001010"; when "1110011001" => sine <= "10111111000101110011000111010001"; cosine <= "00111111010011101001010100001000"; when "1110011010" => sine <= "10111111000101011110110010010101"; cosine <= "00111111010011111000000110001100"; when "1110011011" => sine <= "10111111000101001010010111100110"; cosine <= "00111111010100000110110000001100"; when "1110011100" => sine <= "10111111000100110101110111001001"; cosine <= "00111111010100010101010010001110"; when "1110011101" => sine <= "10111111000100100001010001000000"; cosine <= "00111111010100100011101100000111"; when "1110011110" => sine <= "10111111000100001100100101001111"; cosine <= "00111111010100110001111101111010"; when "1110011111" => sine <= "10111111000011110111110011111000"; cosine <= "00111111010101000000000111101000"; when "1110100000" => sine <= "10111111000011100010111100111111"; cosine <= "00111111010101001110001001000110"; when "1110100001" => sine <= "10111111000011001110000000101000"; cosine <= "00111111010101011100000010011011"; when "1110100010" => sine <= "10111111000010111000111110110101"; cosine <= "00111111010101101001110011011101"; when "1110100011" => sine <= "10111111000010100011110111101001"; cosine <= "00111111010101110111011100001101"; when "1110100100" => sine <= "10111111000010001110101011001001"; cosine <= "00111111010110000100111100101101"; when "1110100101" => sine <= "10111111000001111001011001010110"; cosine <= "00111111010110010010010100110100"; when "1110100110" => sine <= "10111111000001100100000010010101"; cosine <= "00111111010110011111100100100111"; when "1110100111" => sine <= "10111111000001001110100110001001"; cosine <= "00111111010110101100101011111100"; when "1110101000" => sine <= "10111111000000111001000100110101"; cosine <= "00111111010110111001101010110101"; when "1110101001" => sine <= "10111111000000100011011110011100"; cosine <= "00111111010111000110100001010100"; when "1110101010" => sine <= "10111111000000001101110011000001"; cosine <= "00111111010111010011001111010000"; when "1110101011" => sine <= "10111110111111110000000101010010"; cosine <= "00111111010111011111110100101101"; when "1110101100" => sine <= "10111110111111000100011010101101"; cosine <= "00111111010111101100010001100011"; when "1110101101" => sine <= "10111110111110011000100110011001"; cosine <= "00111111010111111000100101110011"; when "1110101110" => sine <= "10111110111101101100101000011101"; cosine <= "00111111011000000100110001011111"; when "1110101111" => sine <= "10111110111101000000100001000000"; cosine <= "00111111011000010000110100011110"; when "1110110000" => sine <= "10111110111100010100010000001001"; cosine <= "00111111011000011100101110110110"; when "1110110001" => sine <= "10111110111011100111110101111110"; cosine <= "00111111011000101000100000011101"; when "1110110010" => sine <= "10111110111010111011010010100111"; cosine <= "00111111011000110100001001010100"; when "1110110011" => sine <= "10111110111010001110100110001011"; cosine <= "00111111011000111111101001011111"; when "1110110100" => sine <= "10111110111001100001110000101111"; cosine <= "00111111011001001011000000110011"; when "1110110101" => sine <= "10111110111000110100110010011100"; cosine <= "00111111011001010110001111010111"; when "1110110110" => sine <= "10111110111000000111101011011000"; cosine <= "00111111011001100001010101000001"; when "1110110111" => sine <= "10111110110111011010011011101010"; cosine <= "00111111011001101100010001110011"; when "1110111000" => sine <= "10111110110110101101000011011010"; cosine <= "00111111011001110111000101110000"; when "1110111001" => sine <= "10111110110101111111100010101101"; cosine <= "00111111011010000001110000101101"; when "1110111010" => sine <= "10111110110101010001111001101011"; cosine <= "00111111011010001100010010110010"; when "1110111011" => sine <= "10111110110100100100001000011100"; cosine <= "00111111011010010110101011110101"; when "1110111100" => sine <= "10111110110011110110001111000101"; cosine <= "00111111011010100000111011110111"; when "1110111101" => sine <= "10111110110011001000001101101111"; cosine <= "00111111011010101011000010111100"; when "1110111110" => sine <= "10111110110010011010000100100000"; cosine <= "00111111011010110101000000111010"; when "1110111111" => sine <= "10111110110001101011110011100000"; cosine <= "00111111011010111110110101110111"; when "1111000000" => sine <= "10111110110000111101011010110101"; cosine <= "00111111011011001000100001101010"; when "1111000001" => sine <= "10111110110000001110111010100111"; cosine <= "00111111011011010010000100010110"; when "1111000010" => sine <= "10111110101111100000010010111101"; cosine <= "00111111011011011011011101111100"; when "1111000011" => sine <= "10111110101110110001100011111111"; cosine <= "00111111011011100100101110010100"; when "1111000100" => sine <= "10111110101110000010101101110010"; cosine <= "00111111011011101101110101100011"; when "1111000101" => sine <= "10111110101101010011110000011111"; cosine <= "00111111011011110110110011100001"; when "1111000110" => sine <= "10111110101100100100101100001101"; cosine <= "00111111011011111111101000010001"; when "1111000111" => sine <= "10111110101011110101100001000010"; cosine <= "00111111011100001000010011110100"; when "1111001000" => sine <= "10111110101011000110001111001000"; cosine <= "00111111011100010000110110000010"; when "1111001001" => sine <= "10111110101010010110110110100011"; cosine <= "00111111011100011001001111000000"; when "1111001010" => sine <= "10111110101001100111010111011101"; cosine <= "00111111011100100001011110101000"; when "1111001011" => sine <= "10111110101000110111110001111100"; cosine <= "00111111011100101001100100111100"; when "1111001100" => sine <= "10111110101000001000000110000111"; cosine <= "00111111011100110001100001111000"; when "1111001101" => sine <= "10111110100111011000010100000111"; cosine <= "00111111011100111001010101011011"; when "1111001110" => sine <= "10111110100110101000011100000010"; cosine <= "00111111011101000000111111101000"; when "1111001111" => sine <= "10111110100101111000011101111111"; cosine <= "00111111011101001000100000011001"; when "1111010000" => sine <= "10111110100101001000011010000111"; cosine <= "00111111011101001111110111110000"; when "1111010001" => sine <= "10111110100100011000010000100000"; cosine <= "00111111011101010111000101101001"; when "1111010010" => sine <= "10111110100011101000000001010010"; cosine <= "00111111011101011110001010000011"; when "1111010011" => sine <= "10111110100010110111101100100100"; cosine <= "00111111011101100101000101000010"; when "1111010100" => sine <= "10111110100010000111010010011110"; cosine <= "00111111011101101011110110011110"; when "1111010101" => sine <= "10111110100001010110110011001000"; cosine <= "00111111011101110010011110011100"; when "1111010110" => sine <= "10111110100000100110001110101000"; cosine <= "00111111011101111000111100110101"; when "1111010111" => sine <= "10111110011111101011001010001101"; cosine <= "00111111011101111111010001101100"; when "1111011000" => sine <= "10111110011110001001101101010101"; cosine <= "00111111011110000101011101000001"; when "1111011001" => sine <= "10111110011100101000000110111000"; cosine <= "00111111011110001011011110101111"; when "1111011010" => sine <= "10111110011011000110010111000101"; cosine <= "00111111011110010001010110111010"; when "1111011011" => sine <= "10111110011001100100011110001010"; cosine <= "00111111011110010111000101011011"; when "1111011100" => sine <= "10111110011000000010011100011000"; cosine <= "00111111011110011100101010010110"; when "1111011101" => sine <= "10111110010110100000010001111011"; cosine <= "00111111011110100010000101101010"; when "1111011110" => sine <= "10111110010100111101111111000101"; cosine <= "00111111011110100111010111010010"; when "1111011111" => sine <= "10111110010011011011100100000101"; cosine <= "00111111011110101100011111010011"; when "1111100000" => sine <= "10111110010001111001000001001000"; cosine <= "00111111011110110001011101100111"; when "1111100001" => sine <= "10111110010000010110010110011111"; cosine <= "00111111011110110110010010001111"; when "1111100010" => sine <= "10111110001110110011100100011001"; cosine <= "00111111011110111010111101001101"; when "1111100011" => sine <= "10111110001101010000101011000101"; cosine <= "00111111011110111111011110011100"; when "1111100100" => sine <= "10111110001011101101101010110010"; cosine <= "00111111011111000011110101111111"; when "1111100101" => sine <= "10111110001010001010100011110000"; cosine <= "00111111011111001000000011110010"; when "1111100110" => sine <= "10111110001000100111010110001110"; cosine <= "00111111011111001100000111110110"; when "1111100111" => sine <= "10111110000111000100000010011010"; cosine <= "00111111011111010000000010001011"; when "1111101000" => sine <= "10111110000101100000101000100101"; cosine <= "00111111011111010011110010101111"; when "1111101001" => sine <= "10111110000011111101001000111110"; cosine <= "00111111011111010111011001100100"; when "1111101010" => sine <= "10111110000010011001100011110100"; cosine <= "00111111011111011010110110100110"; when "1111101011" => sine <= "10111110000000110101111001010111"; cosine <= "00111111011111011110001001110101"; when "1111101100" => sine <= "10111101111110100100010011101010"; cosine <= "00111111011111100001010011010100"; when "1111101101" => sine <= "10111101111011011100101010111101"; cosine <= "00111111011111100100010010111110"; when "1111101110" => sine <= "10111101111000010100111001000101"; cosine <= "00111111011111100111001000110110"; when "1111101111" => sine <= "10111101110101001100111110100010"; cosine <= "00111111011111101001110100111001"; when "1111110000" => sine <= "10111101110010000100111011110001"; cosine <= "00111111011111101100010111001000"; when "1111110001" => sine <= "10111101101110111100110001010010"; cosine <= "00111111011111101110101111100011"; when "1111110010" => sine <= "10111101101011110100011111100011"; cosine <= "00111111011111110000111110001000"; when "1111110011" => sine <= "10111101101000101100000111000100"; cosine <= "00111111011111110011000010111001"; when "1111110100" => sine <= "10111101100101100011101000010100"; cosine <= "00111111011111110100111101110011"; when "1111110101" => sine <= "10111101100010011011000011110000"; cosine <= "00111111011111110110101110110111"; when "1111110110" => sine <= "10111101011110100100110011110010"; cosine <= "00111111011111111000010110000110"; when "1111110111" => sine <= "10111101011000010011010110011011"; cosine <= "00111111011111111001110011011101"; when "1111111000" => sine <= "10111101010010000001110000010111"; cosine <= "00111111011111111011000110111110"; when "1111111001" => sine <= "10111101001011110000000010100110"; cosine <= "00111111011111111100010000101000"; when "1111111010" => sine <= "10111101000101011110001110000101"; cosine <= "00111111011111111101010000011011"; when "1111111011" => sine <= "10111100111110011000100111100100"; cosine <= "00111111011111111110000110010111"; when "1111111100" => sine <= "10111100110001110100101001010110"; cosine <= "00111111011111111110110010011011"; when "1111111101" => sine <= "10111100100101010000100011011100"; cosine <= "00111111011111111111010100100111"; when "1111111110" => sine <= "10111100010001011000101111100111"; cosine <= "00111111011111111111101100111100"; when "1111111111" => sine <= "10111011110000100000100001011001"; cosine <= "00111111011111111111111011011010"; when others => sine <= "00000000000000000000000000000000"; cosine<= "00000000000000000000000000000000"; end case; -- done <= '1'; END PROCESS; END RTL; ------------------------------------------------------------------- -- Copyright 2001 by Howard University All rights reserved. -- -- Design: control_unit for accumulator -- Name: Clay Gloster and Rosie Dickens -- -- Date: Spring 2001 -- Description: This unit is essentially an FSM -- -- ------------------------------------------------------------------- library IEEE; use IEEE.STD_Logic_1164.all; ENTITY acc_control_unit IS PORT ( CLK : in std_logic; RESET : in std_logic; ENABLE : in std_logic; EMPTY : in std_logic; ADDERDONE : in std_logic; ENABLEADDER : out std_logic; LoadR1,LoadR2,LoadR3,LoadR4 : out std_logic; LoadR5,LoadR6,LoadR7,LoadR8 : out std_logic; CTL : out std_logic_vector (2 downto 0); DONE : out std_logic); END acc_control_unit; ARCHITECTURE RTL of acc_control_unit IS type StateType is (Idle,S0,S1,S2, Empty0,Empty1,Empty2,Empty3,Empty4,Empty5,Empty6,Empty7, Empty10,Empty11,Empty12,Empty13,Empty14,Empty15,Empty16,Empty17, Empty20,Empty21,Empty22,Empty23,Empty24,Empty25,Empty26,Empty27, Empty30,Empty31,Empty32,Empty33,Empty34,Empty35,Empty36,Empty37, Empty40,Empty41,Empty42,Empty43,Empty44,Empty45,Empty46,Empty47, Empty50,Empty51,Empty52,Empty53,Empty54,Empty55,Empty56,Empty57, Empty60,Empty61,Empty62,Empty63,Empty64,Empty65,Empty66,Empty67 ); signal CurrentState: StateType; begin FSM_1: process begin wait until clk' EVENT and clk = '1'; --WAIT FOR RISING clk EDGE -- ININTIALIZATION if (Reset = '1') then CurrentState<= Idle; else case (CurrentState) is when Idle=> --machine is now ready to accept inputs if (EMPTY = '0') then CurrentState <= Idle; else CurrentState <= Empty0; -- Got an empty signal end if; when Empty0=> -- Empty the pipe CurrentState <= Empty1; when Empty1=> -- Empty the pipe CurrentState <= Empty2; when Empty2=> -- Empty the pipe CurrentState <= Empty3; when Empty3=> -- Empty the pipe CurrentState <= Empty4; when Empty4=> -- Empty the pipe CurrentState <= Empty5; when Empty5=> -- Empty the pipe CurrentState <= Empty6; when Empty6=> -- Empty the pipe CurrentState <= Empty7; when Empty7=> -- Empty the pipe CurrentState <= Empty10; when Empty10=> -- ADD R1+R2 CurrentState <= Empty11; when Empty11=> -- ADD R3+R4 CurrentState <= Empty12; when Empty12=> -- ADD R5+R6 CurrentState <= Empty13; when Empty13=> -- ADD R7+R8 CurrentState <= Empty14; when Empty14=> -- Empty the pipe CurrentState <= Empty15; when Empty15=> -- Empty the pipe CurrentState <= Empty16; when Empty16=> -- Empty the pipe CurrentState <= Empty17; when Empty17=> -- Empty the pipe CurrentState <= Empty20; when Empty20=> -- Empty the pipe CurrentState <= Empty21; when Empty21=> -- Empty the pipe CurrentState <= Empty22; when Empty22=> -- Empty the pipe CurrentState <= Empty23; when Empty23=> -- Empty the pipe CurrentState <= Empty24; when Empty24=> -- Empty the pipe CurrentState <= Empty25; when Empty25=> -- Empty the pipe CurrentState <= Empty26; when Empty26=> -- Empty the pipe CurrentState <= Empty27; when Empty27=> -- Empty the pipe CurrentState <= Empty30; when Empty30=> -- ADD R1+R2 CurrentState <= Empty31; when Empty31=> -- ADD R3+R4 CurrentState <= Empty32; when Empty32=> -- CurrentState <= Empty33; when Empty33=> -- CurrentState <= Empty34; when Empty34=> -- Empty the pipe CurrentState <= Empty35; when Empty35=> -- Empty the pipe CurrentState <= Empty36; when Empty36=> -- Empty the pipe CurrentState <= Empty37; when Empty37=> -- Empty the pipe CurrentState <= Empty40; when Empty40=> -- Empty the pipe CurrentState <= Empty41; when Empty41=> -- Empty the pipe CurrentState <= Empty42; when Empty42=> -- Empty the pipe CurrentState <= Empty43; when Empty43=> -- Empty the pipe CurrentState <= Empty44; when Empty44=> -- Empty the pipe CurrentState <= Empty45; when Empty45=> -- Empty the pipe CurrentState <= Empty46; when Empty46=> -- Empty the pipe CurrentState <= Empty47; when Empty47=> -- Empty the pipe CurrentState <= Empty50; when Empty50=> -- ADD R1+R2 CurrentState <= Empty51; when Empty51=> CurrentState <= Empty52; when Empty52=> -- CurrentState <= Empty53; when Empty53=> -- CurrentState <= Empty54; when Empty54=> -- Empty the pipe CurrentState <= Empty55; when Empty55=> -- Empty the pipe CurrentState <= Empty56; when Empty56=> -- Empty the pipe CurrentState <= Empty57; when Empty57=> -- Empty the pipe CurrentState <= Empty60; when Empty60=> -- Empty the pipe CurrentState <= Empty61; when Empty61=> -- Empty the pipe CurrentState <= Idle; when others => CurrentState <= Idle; end case; end if; end process FSM_1; outputlogic: process (CurrentState,ENABLE,EMPTY,ADDERDONE) begin case (CurrentState) is when Idle=> --machine is now ready to accept inputs LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "001"; -- Op_Q + Op_A DONE <= '0'; if (ENABLE = '1') AND (EMPTY = '0') then ENABLEADDER <= '1'; else ENABLEADDER <= '0'; end if; when Empty0=> LoadR1 <= '1'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty1=> LoadR1 <= '0'; LoadR2 <= '1'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty2=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '1'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty3=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '1'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty4=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '1'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty5=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '1'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty6=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '1'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty7=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '1'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty10=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "010"; DONE <= '0'; ENABLEADDER <= '1'; when Empty11=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "011"; DONE <= '0'; ENABLEADDER <= '1'; when Empty12=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "100"; DONE <= '0'; ENABLEADDER <= '1'; when Empty13=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "101"; DONE <= '0'; ENABLEADDER <= '1'; when Empty14=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty15=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty16=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty17=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty20=> LoadR1 <= '1'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty21=> LoadR1 <= '0'; LoadR2 <= '1'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty22=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '1'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty23=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '1'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty24=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '1'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty25=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '1'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty26=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '1'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty27=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '1'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty30=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "010"; DONE <= '0'; ENABLEADDER <= '1'; when Empty31=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "011"; DONE <= '0'; ENABLEADDER <= '1'; when Empty32=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty33=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty34=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty35=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty36=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty37=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty40=> LoadR1 <= '1'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty41=> LoadR1 <= '0'; LoadR2 <= '1'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty42=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '1'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty43=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '1'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty44=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '1'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty45=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '1'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty46=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '1'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty47=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '1'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty50=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "010"; DONE <= '0'; ENABLEADDER <= '1'; when Empty51=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty52=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty53=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty54=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty55=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty56=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty57=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty60=> LoadR1 <= '1'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; ENABLEADDER <= '1'; when Empty61=> LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '1'; ENABLEADDER <= '0'; when others => ENABLEADDER <= '0'; LoadR1 <= '0'; LoadR2 <= '0'; LoadR3 <= '0'; LoadR4 <= '0'; LoadR5 <= '0'; LoadR6 <= '0'; LoadR7 <= '0'; LoadR8 <= '0'; CTL <= "000"; DONE <= '0'; end case; end process outputlogic; end RTL; ------------------------------------------------------------------- --Copyright 2001 by Howard University All rights reserved. -- --Design: Register --Name: Clay Gloster -- --Date: June 2001 --Description: -- -- -- ------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_Logic_1164.all; ENTITY reg32 IS PORT(Datain : IN std_logic_vector(31 DOWNTO 0); Load : IN std_logic; Ck : IN std_logic; Reset : IN std_logic; Q : OUT std_logic_vector(31 DOWNTO 0)); END reg32; ARCHITECTURE RTL OF reg32 IS SIGNAL D : std_logic_vector(31 DOWNTO 0); BEGIN PROCESS BEGIN WAIT UNTIL ((Ck'EVENT) AND (Ck= '1')); IF (Reset = '1') THEN -- Changed Reset to Active High D <= "00000000000000000000000000000000"; ELSIF (Load = '1') THEN D <= Datain; ELSE D <= D; END IF; END process; Q <= D; END RTL; ------------------------------------------------------------------- --Copyright 2001 by Howard University All rights reserved. -- --Design: The Input Selector Function for an Accumulator --Name: E. Rose Dickens -- --Date: June 2001 --Description: Non-Generic Module --Inputs include Op_A and Op_Q and Registers whose input will be --32 bit numbers --CTL of this function is a 3 bit number --Input Selector Function is represented as a MUX ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ENTITY InputSelector IS Port(CTL: in std_logic_vector (2 downto 0); -- accepts 3 bit numbers Op_A: in std_logic_vector (31 downto 0); Op_Q: in std_logic_vector (31 downto 0); --also an output of the fp_adder R1: in std_logic_vector (31 downto 0); R2: in std_logic_vector (31 downto 0); R3: in std_logic_vector (31 downto 0); R4: in std_logic_vector (31 downto 0); R5: in std_logic_vector (31 downto 0); R6: in std_logic_vector (31 downto 0); R7: in std_logic_vector (31 downto 0); R8: in std_logic_vector (31 downto 0); CoreLEFT: out std_logic_vector (31 downto 0); CoreRIGHT: out std_logic_vector (31 downto 0)); END; ARCHITECTURE COND_DATA_FLOW OF InputSelector IS BEGIN PROCESS (CTL, Op_A, Op_Q, R1, R2, R3, R4, R5, R6, R7, R8) BEGIN CASE CTL IS when "000" => CoreLEFT <= "00000000000000000000000000000000"; CoreRIGHT <= "00000000000000000000000000000000"; when "001" => CoreLEFT <= Op_Q; CoreRIGHT <= Op_A; when "010" => CoreLEFT <= R1; CoreRIGHT <= R2; when "011" => CoreLEFT <= R3; CoreRIGHT <= R4; when "100" => CoreLEFT <= R5; CoreRIGHT <= R6; when "101" => CoreLEFT <= R7; CoreRIGHT <= R8; when others => CoreLEFT <="--------------------------------"; CoreRIGHT <="--------------------------------"; END CASE; END PROCESS; END COND_DATA_FLOW; ------------------------------------------------------------------- -- Copyright 2001 by NC State University All rights reserved. -- -- Design: Floating Point Accumulator Data Unit -- Name: Clay Gloster -- -- Date: June 2001 -- Description: -- Pipelined. ------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY acc_data_unit IS PORT( clk : IN std_logic; reset : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); LoadR1,LoadR2,LoadR3,LoadR4 : IN std_logic; LoadR5,LoadR6,LoadR7,LoadR8 : IN std_logic; Enable : IN std_logic; CTL : IN std_logic_vector (2 downto 0); EnN : OUT std_logic; Op_Q : OUT std_logic_vector(31 DOWNTO 0)); END acc_data_unit; ARCHITECTURE STRUCTURAL OF acc_data_unit IS component FpAdderCore_8_hold PORT(clk : IN std_logic; reset : IN std_logic; Enable : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); Op_Q : OUT std_logic_vector(31 DOWNTO 0); Done : OUT std_logic); END component; COMPONENT reg32 PORT(Datain : IN std_logic_vector(31 DOWNTO 0); Load : IN std_logic; Ck : IN std_logic; Reset : IN std_logic; Q : OUT std_logic_vector(31 DOWNTO 0)); END COMPONENT; COMPONENT InputSelector Port(CTL: in std_logic_vector (2 downto 0); -- accepts 3 bit numbers Op_A: in std_logic_vector (31 downto 0); Op_Q: in std_logic_vector (31 downto 0); --also an output of the fp_adder R1: in std_logic_vector (31 downto 0); R2: in std_logic_vector (31 downto 0); R3: in std_logic_vector (31 downto 0); R4: in std_logic_vector (31 downto 0); R5: in std_logic_vector (31 downto 0); R6: in std_logic_vector (31 downto 0); R7: in std_logic_vector (31 downto 0); R8: in std_logic_vector (31 downto 0); CoreLEFT: out std_logic_vector (31 downto 0); CoreRIGHT: out std_logic_vector (31 downto 0)); END COMPONENT; SIGNAL CoreLEFT, CoreRIGHT : std_logic_vector(31 DOWNTO 0); SIGNAL R1,R2,R3,R4,R5,R6,R7,R8 : std_logic_vector (31 downto 0); SIGNAL sOp_Q : std_logic_vector (31 downto 0); BEGIN InstR1: reg32 PORT MAP (sOp_Q,LoadR1,clk,reset,R1); InstR2: reg32 PORT MAP (sOp_Q,LoadR2,clk,reset,R2); InstR3: reg32 PORT MAP (sOp_Q,LoadR3,clk,reset,R3); InstR4: reg32 PORT MAP (sOp_Q,LoadR4,clk,reset,R4); InstR5: reg32 PORT MAP (sOp_Q,LoadR5,clk,reset,R5); InstR6: reg32 PORT MAP (sOp_Q,LoadR6,clk,reset,R6); InstR7: reg32 PORT MAP (sOp_Q,LoadR7,clk,reset,R7); InstR8: reg32 PORT MAP (sOp_Q,LoadR8,clk,reset,R8); Instadder: FpAdderCore_8_hold PORT MAP (clk, reset, Enable, CoreLEFT, CoreRIGHT, sOp_Q, EnN); InstMUX: InputSelector port map (CTL,Op_A,sOp_Q,R1,R2,R3,R4,R5,R6,R7,R8,CoreLEFT,CoreRIGHT); Op_Q <= R1; END STRUCTURAL; ------------------------------------------------------------------- --Copyright 2001 by Howard University All rights reserved. -- --Design: Accumulator Core --Name: E. Rose Dickens -- --Date: June 2001 --Description: The inputs on the accumulator will include Op_A, --Enable, and Empty ------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY acc_core IS PORT(clk : IN std_logic; reset : IN std_logic; Op_A : IN std_logic_vector (31 downto 0); ENABLE : IN std_logic; EMPTY : IN std_logic; Op_Q : OUT std_logic_vector (31 downto 0); DONE : OUT std_logic); END acc_core; ARCHITECTURE STRUCTURAL OF acc_core IS COMPONENT acc_control_unit PORT (CLK : in std_logic; RESET : in std_logic; ENABLE : in std_logic; EMPTY : in std_logic; ADDERDONE : in std_logic; ENABLEADDER : out std_logic; LoadR1,LoadR2,LoadR3,LoadR4 : out std_logic; LoadR5,LoadR6,LoadR7,LoadR8 : out std_logic; CTL : out std_logic_vector (2 downto 0); DONE : out std_logic); END COMPONENT; COMPONENT acc_data_unit PORT(clk : IN std_logic; reset : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); LoadR1,LoadR2,LoadR3,LoadR4 : IN std_logic; LoadR5,LoadR6,LoadR7,LoadR8 : IN std_logic; Enable : IN std_logic; CTL : IN std_logic_vector (2 downto 0); EnN : OUT std_logic; Op_Q : OUT std_logic_vector(31 DOWNTO 0)); END COMPONENT; SIGNAL ADDERDONE : std_logic; SIGNAL ENABLEADDER : std_logic; SIGNAL LOADR1 : std_logic; SIGNAL LOADR2 : std_logic; SIGNAL LOADR3 : std_logic; SIGNAL LOADR4 : std_logic; SIGNAL LOADR5 : std_logic; SIGNAL LOADR6 : std_logic; SIGNAL LOADR7 : std_logic; SIGNAL LOADR8 : std_logic; SIGNAL CTL : std_logic_vector (2 downto 0); BEGIN Inst_control: acc_control_unit PORT MAP (clk, reset, ENABLE, EMPTY, ADDERDONE, ENABLEADDER, LOADR1, LOADR2, LOADR3, LOADR4, LOADR5, LOADR6, LOADR7, LOADR8, CTL, DONE); Inst_data: acc_data_unit PORT MAP (CLK, RESET, Op_A, LOADR1, LOADR2, LOADR3, LOADR4, LOADR5, LOADR6, LOADR7, LOADR8, ENABLEADDER, CTL, ADDERDONE, Op_Q); END STRUCTURAL; -- End of Accumulator -------------------------------- -------------------------------------------------------------- -- Copyright 2001 by Howard University All rights reserved. -- -- Design: FunCore -- Name: Generated by FunCoreGen program (Clay Gloster - author) -- -- Date: October 2001 -- Description: PLEASE EDIT -- -- -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use WORK.all; ENTITY NewComplexMult IS PORT( Clk: IN std_logic; Reset: IN std_logic; SelectDFT: IN std_logic; Enable : IN std_logic; Xr : IN std_logic_vector (31 downto 0); Xi : IN std_logic_vector (31 downto 0); CosTheta : IN std_logic_vector (31 downto 0); SinTheta : IN std_logic_vector (31 downto 0); Yr : OUT std_logic_vector (31 downto 0); Yi : OUT std_logic_vector (31 downto 0); DONE : OUT std_logic); END NewComplexMult; -- select DFT zero means FFT ; one means IDFT ARCHITECTURE STRUCTURAL OF NewComplexMult IS Component FixsignR port (S: in std_logic; Datain: in std_logic_vector(31 downto 0); Q: out std_logic_vector(31 downto 0)); end Component; Component FixsignI port (S: in std_logic; Datain: in std_logic_vector(31 downto 0); Q: out std_logic_vector(31 downto 0)); end Component; COMPONENT FpAdderCore_8 PORT( clk : IN std_logic; reset : IN std_logic; EnR : IN std_logic; EnL : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); Op_Q : OUT std_logic_vector(31 DOWNTO 0); EnN : OUT std_logic); END Component; COMPONENT FpMultCore_8 PORT( clk : IN std_logic; reset : IN std_logic; EnR : IN std_logic; EnL : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); Op_Q : OUT std_logic_vector(31 DOWNTO 0); EnN : OUT std_logic); END Component; SIGNAL XrCosTheta : std_logic_vector(31 downto 0); SIGNAL XiSinTheta : std_logic_vector(31 downto 0); SIGNAL XiCosTheta, XrSinTheta : std_logic_vector(31 downto 0); SIGNAL XiSinThetaP, XrSinThetaP : std_logic_vector(31 downto 0); SIGNAL BSIG0, BSIG4, XiSinThetaBar, XrSinThetaBar : std_logic; SIGNAL BSIG1, BSIG5 : std_logic; SIGNAL BSIG2, BSIG6 : std_logic; SIGNAL BSIG3, BSIG7, Donei : std_logic; BEGIN I0: FpMultCore_8 PORT MAP (clk,reset,Enable,Enable,Xr,CosTheta,XrCosTheta,BSIG0); I1: FpMultCore_8 PORT MAP (clk,reset,Enable,Enable,Xi,SinTheta,XiSinTheta,BSIG1); I2: FpMultCore_8 PORT MAP (clk,reset,Enable,Enable,Xi,CosTheta,XiCosTheta,BSIG2); I3: FpMultCore_8 PORT MAP (clk,reset,Enable,Enable,Xr,SinTheta,XrSinTheta,BSIG3); I6: FixsignR PORT MAP (SelectDFT, XiSinTheta, XiSinThetaP); I7: FixsignI PORT MAP (SelectDFT, XrSinTheta, XrSinThetaP); I8: FpAdderCore_8 PORT MAP (clk,reset,BSIG0,BSIG1,XrCosTheta,XiSinThetaP,Yr,Done); I9: FpAdderCore_8 PORT MAP (clk,reset,BSIG2,BSIG3,XiCosTheta,XrSinThetaP,Yi,Donei); END STRUCTURAL; ----------------------------------------------------------- -- Copyright 2002 by Howard University All rights reserved. -- -- Design: Theta Unit Core -- Name: Tiffany Crawford -- -- Date: March 2002 -- Description: Computes the address of the desired sine/ -- -------------------------------------------------------------- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; ENTITY FFT_theta_unit IS PORT(n,k : IN std_logic_vector (9 downto 0); address: OUT std_logic_vector(9 downto 0)); --Will except the remainder of product END FFT_theta_unit; architecture behavioral of FFT_theta_unit is begin PROCESS (n,k) variable product: std_logic_vector(19 DOWNTO 0); BEGIN product:= n*k; address(9 downto 0) <= product(9 downto 0); end process; -- address(9 downto 0) <= product(9 downto 0); end behavioral; ------------------------------------------------------------------- --Copyright 2002 by Howard University All rights reserved. -- --Design: Complex Accumulator Core --Name: Tiffany Crawford -- --Date: March 2002 --Description: The inputs on the complex accumulator will include Real, --Imag, Enable, and Empty ------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY comp_acc_core IS PORT(clk : IN std_logic; reset : IN std_logic; Real : IN std_logic_vector (31 downto 0); Imag : IN std_logic_vector (31 downto 0); ENABLE1 : IN std_logic; EMPTY1 : IN std_logic; RealOut : OUT std_logic_vector (31 downto 0); ImagOut : OUT std_logic_vector (31 downto 0); DONE : OUT std_logic); END comp_acc_core; Architecture structural of comp_acc_core IS Component acc_core PORT(clk : IN std_logic; reset : IN std_logic; Op_A : IN std_logic_vector (31 downto 0); ENABLE : IN std_logic; EMPTY : IN std_logic; Op_Q : OUT std_logic_vector (31 downto 0); DONE : OUT std_logic); END Component; BEGIN I0: acc_core PORT MAP (clk, reset, Real,Enable1 ,Empty1,RealOut,DONE); I1: acc_core PORT MAP (clk, reset, Imag, Enable1 ,Empty1,ImagOut,DONE); End Structural; -------------------------------------------------------------- -- Copyright 2001 by Howard University All rights reserved. --Design Name : FFT Core -- Name: -- Date March, 2002 -- Description : -------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY DFTCore IS PORT (clk : IN std_logic; reset : IN std_logic; Enable: IN std_logic; XR : IN std_logic_vector (31 downto 0); XI, FFTIFFT : IN std_logic_vector (31 downto 0); k : IN std_logic_vector (9 downto 0); empty : IN std_logic; XRealOut : OUT std_logic_vector (31 downto 0); XImagOut : OUT std_logic_vector (31 downto 0); readytoempty : OUT std_logic; DONE : OUT std_logic); END DFTCore; Architecture structural of DFTCore IS Component comp_acc_core PORT(clk : IN std_logic; reset : IN std_logic; Real : IN std_logic_vector (31 downto 0); Imag : IN std_logic_vector (31 downto 0); ENABLE1 : IN std_logic; EMPTY1 : IN std_logic; RealOut : OUT std_logic_vector (31 downto 0); ImagOut : OUT std_logic_vector (31 downto 0); DONE : OUT std_logic); END Component; Component FFT_theta_unit PORT(n,k : IN std_logic_vector (9 downto 0); address: OUT std_logic_vector(9 downto 0)); --Will except the remainder of product END Component; Component FFTsincos_1024 PORT(nk : IN std_logic_vector (9 downto 0); sine, cosine : OUT std_logic_vector(31 downto 0)); End Component; Component Inverter port (A: in std_logic; Q: out std_logic); end Component; Component NewComplexMult PORT( Clk: IN std_logic; Reset: IN std_logic; SelectDFT: IN std_logic; Enable : IN std_logic; Xr : IN std_logic_vector (31 downto 0); Xi : IN std_logic_vector (31 downto 0); CosTheta : IN std_logic_vector (31 downto 0); SinTheta : IN std_logic_vector (31 downto 0); Yr : OUT std_logic_vector (31 downto 0); Yi : OUT std_logic_vector (31 downto 0); DONE : OUT std_logic); END Component; Component COUNTER10 port (Clock, Reset, INC: in std_logic; Q: out std_logic_vector(9 downto 0)); end Component; COMPONENT FpMultCore_8 PORT( clk : IN std_logic; reset : IN std_logic; EnR : IN std_logic; EnL : IN std_logic; Op_A : IN std_logic_vector(31 DOWNTO 0); Op_B : IN std_logic_vector(31 DOWNTO 0); Op_Q : OUT std_logic_vector(31 DOWNTO 0); EnN : OUT std_logic); END Component; SIGNAL SigAddr, n: std_logic_vector(9 downto 0); SIGNAL SigCos : std_logic_vector(31 downto 0); SIGNAL SigSin : std_logic_vector(31 downto 0); SIGNAL SigOut0: std_logic_vector(31 downto 0); SIGNAL SigOut1: std_logic_vector(31 downto 0); SIGNAL SigBOut0, BSIG0: std_logic; SIGNAL SigBOut1, BSIG1: std_logic; SIGNAL XrFFTIFFT : std_logic_vector(31 downto 0); SIGNAL XiFFTIFFT : std_logic_vector(31 downto 0); Signal SelectDFT:std_logic; BEGIN I0: FFT_theta_unit PORT MAP (n, k, SigAddr); I1: FFTsincos_1024 PORT MAP (SigAddr, SigSin, SigCos); I2: NewComplexMult PORT MAP (clk, Reset, SelectDFT, BSIG0, XrFFTIFFT, XiFFTIFFT, SigCos,SigSin, SigOut0, SigOut1, SigBOut0); --Make Bout0 = Bout1 I3: comp_acc_core PORT MAP (clk, Reset, SigOut0, SigOut1, SigBOut0, empty, XRealOut, XImagOut, Done); I4: COUNTER10 PORT MAP (clk, Reset, Enable, n); I5: FpMultCore_8 PORT MAP (clk,reset,Enable,Enable,Xr,FFTIFFT,XrFFTIFFT,BSIG0); I6: FpMultCore_8 PORT MAP (clk,reset,Enable,Enable,Xi,FFTIFFT,XiFFTIFFT,BSIG1); I7:Inverter Port Map(FFTIFFT(26),SelectDFT); readytoempty <= SigBOut0; End structural;