(RARE) Presentations and Publications

Presentations



M. Winder, "Implementation of 2D Discrete Cosine Transform on FPGA Board", HUSEM Research Roundtable, Washington, DC, December 2004. [ html]

C. Gloster and E. Dickens, "A Reconfigurable Instruction Set and Assembler", MAPLD 2002, Laurel, MD, September 2002. [ html]

C. Gloster "Hierarchical Algorithms and Their Embedded Computational Realization in Reconfigurable Hardware", NASA GSFC, Greenbelt, MD., September 2001. [htm]

I. Sahin, C. Gloster, and C. Doss, "The Rare Project", University Booth at 37th Design Automation Conference, Los Angeles, CA., June, 2001. [ppt] [pdf]

I. Sahin, C. Gloster, and C. Doss, "Feasibility of Floating-Point Arithmetic in Reconfigurable Computing Systems", Military and Aerospace Applications of Programmable Devices and Technology Conference, DC., September 2000. [ppt]

I.Sahin, "A Compilation Tool for Automated Mapping of Algorithms Onto FPGA-Based Custom Computing Machines", HiPer DSP Group, Raleigh, NC., Spring 2000. [ppt] [pdf]

S. Subramanian, "High Performance Computing on the Internet", HiPer DSP Group, Raleigh, NC., Spring 2000. [ppt] [pdf]

R. J. Rouse "A Floating Point Divider for RC System", HiPer DSP Group, Raleigh, NC., Spring 2000. [ppt] [pdf]



Journal papers

B. Lent, S. Smith, H. Sheu, J. Schmidt, B. Brenner, C. Gloster, G. Wilikins, L. Schmidt, H. Lyons, and Dana Treistman, "Social Cognitive Predictors of Academic Interests and Goals in Engineering: Utility for Women and Students at Historically Black Universities," Journal of Counseling, 2004, vol. XX no. Y, pp XX-YY. [doc]

W. Alexander, D. Reeves, and C. Gloster, "Parallel Image Processing with the Block Data Parallel Architecture'', (Reprinted from Proceedings of the IEEE, vol. 84, pg 947-968, 1996) IBM Journal of Research and Development , Sept. 2000, vol. 44 no. 5, pp 681-702. [pdf]

M. Figueiredo, C. Gloster, Mark Stephens, Corey Graves, Mouna Nakkar, "Implementation of Multi-spectral Image Classification on a Remote Adaptive Computer", Journal of VLSI Design Special Issue on Reconfigurable Computing, Volume 10, Number 3, pages 307-319, 2000. [pdf]

C. Doss, C. Gloster, "A Distance Education Course in Computer Engineering at NC State University", ASEE Computer in Education Journal, Volume 10, Number 3, pp.22-26 July 2000. [pdf]

W. Alexander, D. Reeves, and C. Gloster, "Parallel Image Processing with the Block Data Parallel Architecture", Proceedings of the IEEE, Volume 84, No. 7, pp. 947-968, July 1996. [pdf]


Theses

H. Phillips, "Design and Implementation of a Reconfigurable Computer for Simulation of Turbulence Induced Flocculation Models", Howard University, M.E. Thesis, May 2003. [pdf]

S. Subramanian, "A Methodology for Mapping Networking Applications to Multiprocessor-FPGA Configurable Computing Systems", NC State University, Ph.D. Thesis, May 2003. [pdf]

I. Sahin, "A Compilation Tool for Automated Mapping of Algorithms onto FPGA-based Custom Computing Machines", NC State University, Ph.D. Thesis, August 2002. [pdf]

C. Doss, "Algorithm Partitioning and Scheduling for Adaptive Computing", NC State University, PhD Dissertation, May 2000. [pdf]

D. Eatmon, "Evaluating Placement Algorithms with the Dream Framework for Reconfigurable Computing Hardware", NC State University, MS Thesis, July 2000. [pdf]

C. Gloster, "Dynamic Scan Testing: A New Paradigm", NC State University, Ph.D. Thesis, March 1993. [ ps Part 1 ] [ ps Part 2 ] [ ps Part 3 ]


Conference papers

S. Subramanian and C. Gloster, "Mapping Network Applications to Multiprocessor-FPGA Configurable Computing Systems", Military and Aerospace Applications of Programmable Devices and Technology Conference, Washington, DC, September 2003. [pdf]

M. White and C. Gloster, "Implementation of the Discrete Fourier Transform on a Reconfigurable Processor", Military and Aerospace Applications of Programmable Devices and Technology Conference, Washington, DC, September 2003. [pdf]

C. Gloster, E. Dickens, "A Reconfigurable Instruction Set Microprocessor", Military and Aerospace Applications of Programmable Devices and Technology Conference, Laurel, MD, September 2002. [pdf]

C. Gloster, H Phillips, "A Reconfigurable Instruction Set and Assembler", NASA Earth Science Techology Conference, Pasadena, California, June 2002. [pdf]

I. Sahin, C. Gloster, and C. Doss, "Feasibility of Floating-Point Arithmetic in Reconfigurable Computing Systems", Military and Aerospace Applications of Programmable Devices and Technology Conference, Greenbelt, MD, September 2000. [pdf]

D. Eatmon, and C. Gloster, "Evaluating Placement Algorithms for Run-Time Reconfigurable Systems", Proceedings of the Military and Aerospace Programmable Logic Devices Conference, Greenbelt, Maryland, Sept. 1999 [doc] [pdf]

C. Doss, and C. Gloster, "Automated Interface Generation for Remote Access to Adaptive Computing Resources", Proceedings of the Military and Aerospace Programmable Logic Devices Conference, Greenbelt, Maryland, Sept. 1999 [doc] [pdf]

C. Graves, C. Gloster, "Advanced Adaptive Wavelet Packet techniques for Image Compression", Accepted for publication in the Proceedings of the International Conference on Signal Processing Applications and Techniques, Dallas, Texas, October 16-19, 2000.

Wensheng Huang, Winser Alexander, Clay Gloster, "Block Wavelet Transform Adaptive Filtering", Proceedings of the First IEEE E/IT Conference, Paper No. EIT 539 Chicago, Illinois, June 8-11, 2000.

M. Figueiredo, C. Gloster, "Implementation of a Probabilistic Neural Network for Multispectral Image Classification on an FPGA Based Custom Computing Machine", 5th Symposium on Neural Networks, Belo Horizonte, Brazil, December 9-11, 1998. [pdf]

C. Doss, C. Gloster, "A Distance Education Course in Computer Engineering at NC State University", Proceedings of the ASEE Conference, Charlotte, NC, June 1999.

Thomas K. Miller, Gary Mirka, Clay Gloster, Cheryl Alderman, Troy Holder, Toby Crawley, Kathy L. Hewitt, Leigh Anne Rettinger, and Catherine E. Brawner. "MBone Virtual Classroom for Engineering Distance Education". 1998 International Conference on Engineering Education, Rio de Janeiro, Brazil, August, 1998.

C. Graves and C. Gloster, "Use of Dynamically Reconfigurable Logic in Adaptive Wavelet Packets", Proceedings of the Canadian Workshop on Programmable Devices, June 1998.

C. Gloster, P. Meyer, and W. Alexander, "Implementing the 2-D Discrete Cosine Transform Using Commercial Quad-Processor DSP Boards", Proceedings of the International Conference on Signal Processing: Applications and Technology, Boston, Massachusetts, October 1996. [pdf]

C. Graves, C. Gloster and C. Doss, "VHDL Modeling of a Parallel Architecture for Computing the Discrete Cosine Transform and it's Inverse", Proceedings of the VHDL International Users Forum, Durham, North Carolina, pp. 63 - 72, October 1996.

C. Gloster and F. Brglez, "Partial Scan Chain Selection for User-Specified Fault Coverage", Proceedings of the European Design Automation Conference, Brighton, United Kingdom, pp. 111 - 116, September 1995. [pdf] [ps] [gz]

C. Gloster and M. Vilas, "Automatic Built-In Self-Test Insertion for High Level Circuit Descriptions", Proceedings of the IEEE ASICs Conference, Austin, Texas, pp. 222-226, September 1995. [pdf]

C. Gloster and S. Subramanian, "A Fault Coverage-Driven Partial Scan Chain Selection Technique", Proceedings of the IEEE ASICs Conference, Rochester, N.Y., pp. 366-369 September 1994. [pdf]

C. Gloster, F. Brglez, "Synthesis of Weighted Random Sequences with Application to Testing of Sequential Circuits", Proc. of the EDAC-EUROASIC-1993, Paris, France, pp. 231-237, February 1993. [pdf] [ps]

C. Gloster, F. Brglez, "Cellular Scan Test Generation for Sequential Circuits", Proc. of the European Design Automation Conference, Hamburg, Germany, pp. 530- 536, September 1992. [pdf]

C. Gloster, F. Brglez, "Cellular Scan Revisited", Proc. of the Third Annual Symposium on CSA and the Twenty-Fourth Southeastern Symposium on System Theory, pp. 246-250, March 1992. [pdf]

C. Gloster, F. Brglez, "Synthesis for BIST of Finite State Machines", Proc. of the Second Annual Symposium on CSA, pp. 155-160, March 1991.

C. Gloster, F. Brglez, "Boundary Scan with Built-In Self-Test", Reprinted In Book: C. Maunder and R. Tulloss, The Test Access Port and Boundary Scan Architecture, pp. 266 - 274, September 1990.

F. Brglez, C. Gloster, G. Kedem, "Built-In Self-Test with Weighted Random Pattern Hardware", Proc. of the International Conference on Computer Design, pp. 161-166, September 1990. [pdf]

F. Brglez, C. Gloster, G. Kedem, "Hardware Based Weighted Random Pattern Generation for Boundary Scan", Proc. of the IEEE International Test Conference, August 1989. [pdf]

F. Brglez, D. Bryan, C. Gloster, G. Kedem, K. Kozminski, R. Lisanke, M. Schulz, "Synergy of Synthesis and Test", Proc. of the Univ./Govt./Industry Microelectronics Symposium, June 1989. [pdf]

C. Gloster, F. Brglez, "Boundary Scan with Built-In Self-Test", IEEE Design and Test of Computers, Volume 6, Number 1, pp. 36-44, February 1989. [pdf]

C. Gloster, F. Brglez, "Boundary Scan with Cellular-Based Built-In Self-Test", Revised and Reprinted In: S. Scheiber, "Building Circuits that Test Themselves", Test and Measurement World, Volume 8, Number 11, pp. 60-68, November 1988.

C. Gloster, F. Brglez, "Boundary Scan with Cellular-Based Built-In Self-Test", Proc. of the IEEE International Test Conference, September 1988. [pdf]