Department of Electrical & Computer Engineering
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Homework 4
3.5) In the following table, write whether each type of transistor will act as an open circuit or a closed circuit.
|
Gate |
n-type |
p-type |
|
Gate = 1 |
|
|
|
Gate = 0 |
|
|
3.7)� The circuit shown in problem 3.7 of the textbook has a major flaw.� Can you identify it? Hint: Evaluate the circuit for all sets of inputs.
3.9)� Fill in the truth table for the logical expression NOT ( NOT(A) OR NOT(B) ).�
What single logic gate has the same truth table?
|
A |
B |
NOT (NOT (A) OR NOT (B)) |
|
0 |
0 |
|
|
0 |
1 |
|
|
1 |
0 |
|
|
1 |
1 |
|
3.12)� Following the example of Figure 3.111a, draw the gate level schematic of a three input decoder.� For each output of this decoder, write the input conditions under which that output will be one.
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3.13) How many output lines will a five-input decoder have?
3.18) Implement the following functions using AND, OR, and NOT logic gates.� The inputs are A,B, and the output is F.
a. F has the value 1 only if A has the value 0 and B has the value 1.
b. F has the value 1 only if A has the value 1 and B has the value 0.
c. Use your answers from a and b to implement a 1-bit adder.� The truth table for a 1-bit adder is shown below.
|
A |
B |
Sum |
|
0 |
0 |
0 |
|
0 |
1 |
1 |
|
1 |
0 |
1 |
|
1 |
1 |
0 |
d. Is it possible to create a 4-bit adder (a circuit that will correctly add two 4-bit quantities) using only four copies of the logic diagram from c?� If not, what information is missing? Hint: When A=1 and B=1, a sum of 0 is produced.� What information is dropped?
3.21) You know that a byte is 8 bits.� We call a 4-bit quantity a nibble. If a byte-addressable memory has a 14-bit address, how many nibbles of storage are in this memory?
3.23) Given the logic circuit in Figure 3.38 on page 88 of the textbook, fill in the truth table for the output value Z.
|
A |
B |
C |
Z |
|
0 |
0 |
0 |
|
|
0 |
0 |
1 |
|
|
0 |
1 |
0 |
|
|
0 |
1 |
1 |
|
|
1 |
0 |
0 |
|
|
1 |
0 |
1 |
|
|
1 |
1 |
0 |
|
|
1 |
1 |
1 |
|
3.25) Say the speed of a logic structure depends on the largest number of logic gates through which any of the inputs must propagate to reach an output.� Assume that a NOT, and AND, and an OR gate all count as one gate delay.� For example, the propagation delay for a two input decoder shown in Figure 3.11 is 2 because some inputs propagate through a maximum of 2 gates on a path from input to output.
���� a. What is the propagation delay for the two input mux shown in Figure 3.12?
���� b. What is the propagation delay 1-bit full adder shown in Figure 3.15?
���� c. What is the propagation delay for the 4-bit adder shown in Figure 3.16?
���� d. What if the 4-bit adder were extended to 32 bits? What is the propagation delay?
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3.33) Using Figure 3.21, the diagram of the 4-entry, 22 by 3-bit memory.
a. To read from the fourth memory locations, what must the values of A[1:0] and WE be?
b. To change the number of entries in the memory from 4 to 60, how many address lines would be needed?� What would the addressability of the memory be after this change was made?
c. Suppose the minimum width (in bits) of the program counter� is the minimum number of bits needed to address all 60 locations in our memory of part b. How many additional memory location could be added to this memory without having to alter the width of the program counter?