-- 
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design: A Row of an Integer Divider  
-- Name:    Tiffany Crawford and Clay Gloster
--      
-- Date:    May 2001
-- Description: Generic Module 
--  N is the width of the numerator and denominators
--  Produces one output bit Q
--------------------------------------------------------------
       library IEEE; 
       use IEEE.std_logic_1164.all;
       use IEEE.std_logic_arith.all;
       use IEEE.std_logic_unsigned."-";
       use IEEE.std_logic_unsigned.">";
       use IEEE.std_logic_unsigned."=";
       entity row_generic is      --Declare a row with N cells
       generic  (N: integer); 
         port( NUM: in std_logic_vector(N-1 downto 0); 
               DEN : in std_logic_vector (N-1 downto 0); 
               DIFF : out std_logic_vector(N-1 downto 0); 
               DIV_OUT: out std_logic_vector(N-1 downto 0); 
               Q : out std_logic ); 
       end row_generic; 
       architecture functional of row_generic is 
        begin
        process(NUM,DEN)
        begin
        IF (NUM >= DEN) then DIFF <= NUM - DEN;
        Q <= '1';
        else
        DIFF <= NUM;
        Q <= '0';
        end if;
        DIV_OUT <= DEN;
        end process;
       end functional;
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design: A Connect Module that connects two rows of an integer divider
-- Name:    Tiffany Crawford and Clay Gloster
--      
-- Date:    May 2001
-- Description: Generic Module 
--  N is the width of the inputs and outputs
--  Passes div_out to den for the next row
--  Shifts diff for use in the next row numerator.
--------------------------------------------------------------
        library IEEE;
        use IEEE.std_logic_1164.all;
        entity row_connect is             --Connects the rows 
      generic (N : integer);
        port (DIFF: in std_logic_vector(N-1 downto 0);
                DIV_OUT: in std_logic_vector(N-1 downto 0);
            NUM: out std_logic_vector(N-1 downto 0);
                DEN: out std_logic_vector(N-1 downto 0));
        end row_connect;
      architecture structural of row_connect is
        begin
     lpp1: for i in N-1 downto 1 generate  --Connects left side of the array
                NUM(i) <= DIFF(i-1);
      end generate;
                NUM(0) <= '0';
        lpp2: for i in N-1 downto 0 generate          --Connects right side of array
                DEN (i) <= DIV_OUT(i);  
        end generate;
        end structural;
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design: A Connect Module that connects the FIRST TWO rows of an integer divider
-- Name:    Tiffany Crawford and Clay Gloster
--      
-- Date:    May 2001
-- Description: Generic Module 
--  N is the width of the inputs and outputs
--  Passes div_out to den for the next row
--  Shifts diff for use in the next row numerator.
--------------------------------------------------------------
library IEEE;
        use IEEE.std_logic_1164.all;
        entity first_row_connect is             --Connects the rows 
      generic (N : integer);
        port (DIFF: in std_logic_vector(N-1 downto 0);
                DIV_OUT: in std_logic_vector(N-1 downto 0);
            NUM: out std_logic_vector(N downto 0);
            DEN: out std_logic_vector(N downto 0) );
        end first_row_connect;
      architecture behavioral of first_row_connect is
        begin
      lpp1: for i in N downto 1 generate   --Connects left side of array
                NUM(i) <= DIFF(i-1);
      end generate;
                NUM(0) <= '0';
       DEN(N) <= '0'; 
        lpp2: for j in N-1 downto 0 generate   --  Connects right side of array
                DEN (j) <= DIV_OUT(j);  
        end generate;
        end behavioral;
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design: The first row and interconnect of an integer divider
-- Name:    Tiffany Crawford and Clay Gloster
--      
-- Date:    May 2001
-- Description: Generic Module 
--  N is the width of the numerator and denominator
--  Outputs connecting to the second row are N+1 bits wide.
--  Produces one bit of the quotient.
--------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Carries out first row of division
entity first_row_divider is
generic (N: integer);
port(NUM: in std_logic_vector(N-1 downto 0); 
     DEN: in std_logic_vector(N-1 downto 0);
     NUM1: out std_logic_vector(N downto 0);
     DEN1: out std_logic_vector(N downto 0);
     Q: out std_logic );
end first_row_divider;
architecture structural of first_row_divider is
component row_generic
generic(N: INTEGER);
port( NUM : in std_logic_vector(N-1 downto 0); 
            DEN : in std_logic_vector (N-1 downto 0); 
            DIFF : out std_logic_vector(N-1 downto 0); 
            DIV_OUT: out std_logic_vector(N-1 downto 0); 
      Q : out std_logic );
end component;
component first_row_connect 
      generic (N : integer);
        port (DIFF: in std_logic_vector(N-1 downto 0);
                DIV_OUT: in std_logic_vector(N-1 downto 0);
            NUM: out std_logic_vector(N downto 0);
            DEN: out std_logic_vector(N downto 0) );
end component;
signal SDIFF1,SDIV_OUT1:
             STD_LOGIC_VECTOR(N-1 DOWNTO 0);
        begin
         U0: row_generic generic map(N)
     port map(NUM,DEN, SDIFF1, SDIV_OUT1,Q); 
       U1: first_row_connect generic map(N) 
           port map(SDIFF1, SDIV_OUT1, NUM1, DEN1);
        end structural;
--------------------------------------------------------------------------------
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design: A block of an integer divider (not including the first row.)
-- Name:    Tiffany Crawford and Clay Gloster
--      
-- Date:    May 2001
-- Description: Generic Module 
--  N is the width of the numerator and denominator (combinational logic)
--  Passes DEN to DIV_OUT for the next block of the divider
--------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity block_generic is
generic (M, N: integer);
port(NUM: in std_logic_vector(N-1 downto 0); 
     DEN: in std_logic_vector(N-1 downto 0);
     DIFF: out std_logic_vector(N-1 downto 0);
     DIV_OUT: out std_logic_vector(N-1 downto 0);
     Q: out std_logic_vector(M-1 downto 0));
end block_generic;
architecture structural of block_generic is
component row_connect 
      generic (N : integer);
        port (DIFF: in std_logic_vector(N-1 downto 0);
            DIV_OUT: in std_logic_vector(N-1 downto 0);
            NUM: out std_logic_vector(N-1 downto 0);
            DEN: out std_logic_vector(N-1 downto 0));
end component; 
component row_generic
generic(N: INTEGER);
port( NUM : in std_logic_vector(N-1 downto 0); 
            DEN : in std_logic_vector (N-1 downto 0); 
            DIFF : out std_logic_vector(N-1 downto 0); 
            DIV_OUT: out std_logic_vector(N-1 downto 0); 
      Q : out std_logic );
end component;
type sig2d is array (0 to M) of std_logic_vector (N-1 downto 0);
signal SNUM,SDEN : sig2d; 
signal SDIFF, SDIV_OUT: sig2d;
        begin
        --Carries out remaining rows
      lpp1: for i in M downto 1 generate       --Produces an M bit Quotient
UNA: row_generic generic map (N)
     port map( SNUM(i),SDEN(i),SDIFF(i),SDIV_OUT(i),Q(i-1)); 
UNB: row_connect generic map(N)
     port map(SDIFF(i),SDIV_OUT(i),SNUM(i-1),SDEN(i-1) );
     end generate;
        SNUM(M)<= NUM;                
      SDEN(M) <= DEN;
      DIFF<= SNUM(0);                
      DIV_OUT <= SDEN(0);
end structural;
--------------------------------------------------------------------------------
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design: A generic combinational integer divider
-- Name:    Tiffany Crawford and Clay Gloster
--      
-- Date:    May 2001
-- Description: Generic Module 
--  N is the width of the numerator and denominator
--  M is the width of the quotient 
--  Passes dif and div_out to ouput for the next block
--  --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity generic_divider is
generic (M, N: integer);
port(NUM: in std_logic_vector(N-1 downto 0); 
     DEN: in std_logic_vector(N-1 downto 0);
     DIFF: out std_logic_vector(N downto 0);
     DIV_OUT: out std_logic_vector(N downto 0);
     Q: out std_logic_vector(M-1 downto  0));
end generic_divider;
architecture structural of generic_divider is
component first_row_divider
generic (N: integer);
port(NUM: in std_logic_vector(N-1 downto 0); 
     DEN: in std_logic_vector(N-1 downto 0);
     NUM1: out std_logic_vector(N downto 0);
     DEN1: out std_logic_vector(N downto 0);
     Q: out std_logic );
end component;
component block_generic
generic (M, N: integer);
port(NUM: in std_logic_vector(N-1 downto 0); 
     DEN: in std_logic_vector(N-1 downto 0);
     DIFF: out std_logic_vector(N-1 downto 0);
     DIV_OUT: out std_logic_vector(N-1 downto 0);
     Q: out std_logic_vector(M-1 downto 0));
end component;
signal SNUM1,SDEN1: std_logic_vector (N downto 0);
signal TQ: std_logic;
signal TTQ: std_logic_vector(M-2 downto 0); 
begin
         --Carries out first row
U0: first_row_divider 
     generic map(N)
     port map(NUM,DEN,SNUM1,SDEN1,TQ); 
UNA:  block_generic 
      generic map (M-1, N+1)
      port map (SNUM1, SDEN1, DIFF, DIV_OUT, TTQ);
        --Carries out remaining rows
      lpp1: for i in M-2 downto 0 generate       --Produces an M bit Quotient
       Q(i) <= TTQ(i);     
        end generate;
        Q(M-1)<= TQ;
end structural;
---------------------------------------------------------------
--Copyright 2001 by Howard University All rights reserved.
--
--Design: Generic Register
--Name: Clay Gloster
--
--Date: May 2001
--Description:  Generic Register
--Width equal to one
--Does not have parallel
---------------------------------------------------------------
library IEEE;
use IEEE.STD_Logic_1164.all;
entity REG_GENERIC is
generic (Width : integer);
port (Datain : in std_logic_vector(Width-1 downto 0);
Clk,Reset : in std_logic;
Q: out std_logic_vector(Width-1 downto 0) );
end REG_GENERIC;
architecture RTL of REG_GENERIC is
begin
start: process(Clk)
variable i: integer;
begin
if (Clk'EVENT and Clk = '1') then
 if (Reset = '1') then  -- Changed Reset to Active High
  for i in 0 to Width-1 loop
   Q(i) <= '0';
  end loop;
 else
 Q <= Datain;
 end if;
end if;
end process;
end RTL;
---------------------------------------------------------------
--Copyright 2001 by Howard University All rights reserved.
--
--Design: 2 Dimensional Shift Register
--Name: Clay Gloster
--
--Date: May 2001
--Description:
--
--
---------------------------------------------------------------
library IEEE;
use IEEE.STD_Logic_1164.all;
entity register2d is
generic (Height, Width : integer);
port (Datain : in std_logic_vector(Width-1 downto 0);
Clk,Reset : in std_logic;
Q: out std_logic_vector(Width-1 downto 0) );
end register2d;
architecture structural of register2d is
component REG_GENERIC
  generic (Width : integer);
  port (Datain : in std_logic_vector(Width-1 downto 0);
        Clk,Reset : in std_logic;
        Q: out std_logic_vector(Width-1 downto 0) );
end component;
type anarray is array ( 0 to Height) of std_logic_vector(Width-1 downto 0);
signal REGIO : anarray;
begin
 lpp1: for i in  0 to Height-1 generate
 I0:   REG_GENERIC generic map (Width)
       port map ( REGIO(i), Clk, Reset, REGIO(i+1) );
        end generate;
 REGIO(0) <= Datain;
 Q <= REGIO(Height);
end structural;
---------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Pipelines the divider
entity pipelined_divider is
generic (M : integer := 30;
         N : integer := 24;
                 P: integer  := 15);
port(NUM: in std_logic_vector(N-1 downto 0); 
     DEN: in std_logic_vector(N-1 downto 0);
     Reset,Clk : in std_logic;
     Q: out std_logic_vector(M-1 downto 0) );
end pipelined_divider;
architecture structural of pipelined_divider is
---  K = M/P                     (defines K)
component generic_divider
generic (M, N: integer);
port(NUM: in std_logic_vector(N-1 downto 0); 
     DEN: in std_logic_vector(N-1 downto 0);
     DIFF: out std_logic_vector(N downto 0);
     DIV_OUT: out std_logic_vector(N downto 0);
     Q: out std_logic_vector(M-1 downto 0) );
end component;
component block_generic
generic (M, N: integer);
port(NUM: in std_logic_vector(N-1 downto 0); 
     DEN: in std_logic_vector(N-1 downto 0);
     DIFF: out std_logic_vector(N-1 downto 0);
     DIV_OUT: out std_logic_vector(N-1 downto 0);
     Q: out std_logic_vector(M-1 downto 0));
end component;
component reg_generic           
generic (Width : integer);
port (Datain : in std_logic_vector(Width-1 downto 0);
Clk, Reset : in std_logic;
Q: out std_logic_vector(Width-1 downto 0) );
end component;
component register2d
generic (height, width: integer);
port (Datain : in std_logic_vector(Width-1 downto 0);
      Clk, Reset : in std_logic;
      Q: out std_logic_vector(Width-1 downto 0) );
end component;
type anothersignal2d is array (P downto 1) of std_logic_vector((M/P) -1 downto 0);
        signal TQ,TTQ: anothersignal2d;
        signal SDIFF, SDIV_OUT: std_logic_vector  (N downto 0);
type signal2d is array (P-1 downto 0) of std_logic_vector (N downto 0);
signal SNUM,SDEN, SDIFF1, SDIV_OUT1: signal2d; 
      begin
        UO: generic_divider 
        generic map (M/P, N)
        port map (NUM, DEN, SDIFF, SDIV_OUT, TQ(P));
        U1: reg_generic
        generic map (N+1)
        port map (SDIFF, Clk, Reset, SNUM(P-1));        
        U2: reg_generic
        generic map (N+1)
        port map (SDIV_OUT, Clk, Reset, SDEN(P-1));     
        U3: register2d 
        generic map (P,M/P)
        port map (TQ(P), Clk, Reset, TTQ(P)); 
        lpp1: for i in P-1 downto 1 generate
        U4: block_generic generic map(M/P, N+1)
        port map (SNUM(i), SDEN(i), SDIFF1(i), SDIV_OUT1(i), TQ(i));
        U5: reg_generic
        generic map (N+1)
        port map(SDIFF1(i), Clk, Reset, SNUM(i-1));     
        U6: reg_generic
        generic map (N+1)
        port map(SDIV_OUT1(i), Clk, Reset, SDEN(i-1));  
        U7: register2d 
        generic map (i,M/P)
        port map(TQ(i), Clk, Reset, TTQ(i)); --Do the clock and reset
        end generate;
lpp3: for i in P-1 downto 0 generate
lpp2: for j in (M/P)-1 downto 0 generate
 Q( ((M/P)*i)+j )<= TTQ(i+1)(j);
end generate;
end generate;
-- Q(0) <= TTQ(1)(0);
end structural;
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
-- Check for Divide by Zero Error Unit In the Floating Point Divider
-- Name:    Clay Gloster and Rosie Dickens
--      
-- Date:    May 2001
-- Description:
-- 
--------------------------------------------------------------
library IEEE;
use IEEE.STD_Logic_1164.all;
entity StageDBZ is
port (Datain : in std_logic_vector(31 downto 0);
Clk,Reset : in std_logic;
Q: out std_logic);
end StageDBZ;
architecture RTL of StageDBZ is
begin
start: process(Clk)
begin
if (Clk'EVENT and Clk = '1') then
 if (Reset = '1') then  -- Changed Reset to Active High
  	Q <= '0';
 else
	if ( Datain = "00000000000000000000000000000000") then
 	Q <= '1';
	else
	Q <= '0';
	end if;
 end if;
end if;
end process;
end RTL;
library IEEE;
use IEEE.STD_Logic_1164.all;
entity dividebyzero is
port (Datain : in std_logic_vector(31 downto 0);
Clk,Reset : in std_logic;
Q: out std_logic );
end dividebyzero;
architecture structural of dividebyzero is
component register2d
generic (Height, Width : integer);
port (Datain : in std_logic_vector(Width-1 downto 0);
Clk,Reset : in std_logic;
Q: out std_logic_vector(Width-1 downto 0) );
end component;
component StageDBZ
port (Datain : in std_logic_vector(31 downto 0);
Clk,Reset : in std_logic;
Q: out std_logic);
end component;
signal Serror : std_logic;
signal VSerror,VSQ : std_logic_vector(0 downto 0);
begin
 I0:   StageDBZ  port map (Datain,Clk,Reset,Serror);
 I1:   register2d generic map(6,1)
       port map (VSerror,Clk,Reset,VSQ);
VSerror(0) <= Serror;
Q <= VSQ(0);
end structural;
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
-- Subtract Exponents Floating Point Divider
-- Name:    Clay Gloster
--      
-- Date:    May 2001
-- Description:
--  
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."*";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY SubExp IS
        PORT(clk        : in std_logic;
                reset: in std_logic;
                EnR     : in std_logic;
                EnL     : in std_logic;
                Exp_A: in std_logic_vector(7 downto 0);
                Exp_B: in std_logic_vector(7 downto 0);
                SignA: in std_logic;
                SignB: in std_logic;
                Exp     : out std_logic_vector(7 downto 0); 
                Sign : out std_logic;
                RunO    : out std_logic);
END SubExp;
ARCHITECTURE RTL OF SubExp IS
BEGIN
        PROCESS (CLK,reset)
                variable ExpAPrime : std_logic_vector(7 downto 0);
        BEGIN
                IF (clk = '1' and clk'event) THEN
                        IF (reset = '1') THEN
                                Exp <= (Others=> '0');
                                Sign <= '0';
                                RunO <= '0';
                        ELSE 
                                RunO <= EnR and EnL;
                                IF (EnR = '1' and EnL = '1') THEN
                                        ExpAPrime := Exp_A - Exp_B;
                                        Exp <= "01111111" + ExpAPrime;-- Need to add 127 
                                        Sign <= SignA XOR SignB;
                                END IF; -- END IF Run= '1'
                        END IF; -- END IF reset = 0
                END IF; -- END IF clk = '1' and clk'event
        END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 2000 by Howard University All rights reserved.
--
-- Design: 9 bit register
-- Name:    Clay Gloster
--      
-- Date:    April 2000
-- Description:
--  Pipelined.
--------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_Logic_1164.all;
ENTITY Divreg10 IS
        PORT(Datain     : IN std_logic_vector(8 DOWNTO 0);
                Ck              : IN std_logic;
                Reset   : IN std_logic;
                Run             : IN std_logic;
                Q               : OUT std_logic_vector(8 DOWNTO 0);
                RunO            : OUT std_logic);
END Divreg10;
ARCHITECTURE RTL OF Divreg10 IS
        SIGNAL D : std_logic_vector(8 DOWNTO 0);
BEGIN
        PROCESS
        BEGIN
                WAIT UNTIL ((Ck'EVENT) AND (Ck= '1'));
                IF (Reset = '1') THEN            -- Changed Reset to Active High
                        D <= "000000000";
                        RunO <= '0';
                ELSE
                        RunO <= Run;
                        IF (Run = '1') THEN
                                D <= Datain;
                        ELSE
                                D <= D;
                        END IF;
                END IF ;
        END process;
        Q <= D;
END RTL;
--------------------------------------------------------------
-- Copyright 2001 by Howard University All rights reserved.
--
-- Design: Floating Point Adder
-- Name:    Ibrahim Sahin and Clay Gloster
--      
-- Date:    June 2001
-- Description:
--  Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.">";
use IEEE.std_logic_unsigned.SHL;
use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR;
ENTITY DivNorm1 IS
         PORT(clk                :  IN std_logic;
                reset   :  IN std_logic;
                Run             :  IN std_logic;
                UMan            :  IN std_logic_vector (29 Downto 0);
                UExp            :  IN std_logic_vector ( 8 DOWNTO 0);
		        ZError		:  IN std_logic;
                Result  : OUT std_logic_vector (31 DOWNTO 0);
                RunO            : OUT std_logic);
END DivNorm1;
ARCHITECTURE RTL OF DivNorm1 IS
BEGIN
        PROCESS (CLK,reset)
                variable ExpPrime : std_logic_vector(7 downto 0);
		variable TMan : std_logic_vector(22 downto 0);
        BEGIN
                IF (clk = '1' and clk'event) THEN
                        IF (reset = '1') THEN
                                Result <= (OTHERS  => '0');
				RunO <= '0';
                        ELSE
                        RunO <= Run;
                        IF ( (Run = '1') and (ZError = '0') and (UMan(29) = '1') ) THEN
                            Result(31) <= UExp(8);
			    -- No need to adjust exponents
                            Result(30 DOWNTO 23) <= UExp(7 DOWNTO 0);																  
                            TMan := Uman(28 DOWNTO 6);
			    IF ( (UMan(6) = '1') AND (UMan(5) = '1') ) THEN
			      TMan := Tman + 1;
			    END IF;
			Result(22 DOWNTO 0) <= TMan;
			END IF;
			IF ( (Run = '1') and (ZError = '0') and (UMan(29) = '0') ) THEN
                            Result(31) <= UExp(8);
			    -- We need to adjust exponents
			    ExpPrime := UExp(7 DOWNTO 0);
                            Result(30 DOWNTO 23) <= ExpPrime - "00000001"; -- Subtract one
			    TMan := Uman(27 DOWNTO 5);
			    IF ( (UMan(5) = '1') AND (UMan(4) = '1') ) THEN
			      TMan := Tman + 1;
			    END IF;
			Result(22 DOWNTO 0) <= TMan;
			END IF;																	
			IF ( (Run = '1') and (ZError = '1') ) THEN
			    Result <= "11111111111111111111111111111111"; -- Divide By Zero Error
			END IF;	
		END IF; -- End if reset = 1																 
		END IF;
	END PROCESS;
END RTL;
--------------------------------------------------------------
-- Copyright 2000 by Howard University All rights reserved.
--
-- Design:      Floating Point Divider Core
-- Name:                Clay Gloster
--      
-- Date:    May 2001
-- Description:
-- Pipelined.
--------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
ENTITY FpDivCore_16 IS
        PORT(clk                : IN std_logic;
                reset   : IN std_logic;
                EnR             : IN std_logic;
                EnL             : IN std_logic;
                Op_A            : IN std_logic_vector(31 DOWNTO 0);
                Op_B            : IN std_logic_vector(31 DOWNTO 0);
                Op_Q            : OUT std_logic_vector(31 DOWNTO 0);
                EnN             : OUT std_logic);
END FpDivCore_16;
ARCHITECTURE STRUCTURAL OF FpDivCore_16 IS
COMPONENT SubExp
        PORT(clk        : in std_logic;
                reset: in std_logic;
                EnR     : in std_logic;
                EnL     : in std_logic;
                Exp_A: in std_logic_vector(7 downto 0);
                Exp_B: in std_logic_vector(7 downto 0);
                SignA: in std_logic;
                SignB: in std_logic;
                Exp     : out std_logic_vector(7 downto 0); 
                Sign : out std_logic;
                RunO    : out std_logic);
END COMPONENT;
COMPONENT Divreg10
        PORT(Datain     : IN std_logic_vector(8 DOWNTO 0);
                Ck              : IN std_logic;
                Reset   : IN std_logic;
                Run             : IN std_logic;
                Q               : OUT std_logic_vector(8 DOWNTO 0);
                RunO            : OUT std_logic);
END COMPONENT;
COMPONENT pipelined_divider
        generic (M : integer := 28;
         N : integer := 24;
                 P: integer  := 7);
port(NUM: in std_logic_vector(N-1 downto 0); 
     DEN: in std_logic_vector(N-1 downto 0);
     Reset,Clk : in std_logic;
     Q: out std_logic_vector(M-1 downto 0) );
END COMPONENT;
COMPONENT DivNorm1
        PORT(clk                :  IN std_logic;
                reset   :  IN std_logic;
                Run             :  IN std_logic;
                UMan            :  IN std_logic_vector (29 Downto 0);
                UExp            :  IN std_logic_vector ( 8 DOWNTO 0);
		        ZError		:  IN std_logic;
                Result  : OUT std_logic_vector (31 DOWNTO 0);
                RunO            : OUT std_logic);
END COMPONENT;
COMPONENT RegStage8
        PORT(Clk         : IN std_logic;
                Reset   : IN std_logic;
                Run             : IN std_logic;
                Datain  : IN std_logic_vector(31 DOWNTO 0);
                Q               : OUT std_logic_vector(31 DOWNTO 0);
                RunO            : OUT std_logic);
END COMPONENT;
COMPONENT DivideByZero
		PORT (Datain : in std_logic_vector(31 downto 0);
			Clk,Reset : in std_logic;
				Q: out std_logic );
END COMPONENT;
SIGNAL Exp1_2    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp2_3    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp3_4    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp4_5    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp5_6    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp6_7    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp7_8    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp8_9    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp9_10    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp10_11    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp11_12    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp12_13    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp13_14    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp14_15    : std_logic_vector (8 DOWNTO 0);
SIGNAL Exp15_16    : std_logic_vector (8 DOWNTO 0);
SIGNAL RunO1_2   : std_logic;
SIGNAL RunO2_3   : std_logic;
SIGNAL RunO3_4   : std_logic;
SIGNAL RunO4_5   : std_logic;
SIGNAL RunO5_6   : std_logic;
SIGNAL RunO6_7   : std_logic;
SIGNAL RunO7_8   : std_logic;
SIGNAL RunO8_9   : std_logic;
SIGNAL RunO9_10   : std_logic;
SIGNAL RunO10_11   : std_logic;
SIGNAL RunO11_12   : std_logic;
SIGNAL RunO12_13   : std_logic;
SIGNAL RunO13_14   : std_logic;
SIGNAL RunO14_15   : std_logic;
SIGNAL RunO15_16   : std_logic;
SIGNAL Result15_16: std_logic_vector (29 DOWNTO 0);
SIGNAL ZError   : std_logic;
SIGNAL Op_A01,Op_B01 :std_logic_vector(23 downto 0);
BEGIN
        Inst_Exp: SubExp PORT MAP(clk,reset,EnR,EnL,Op_A(30 DOWNTO 23),Op_B(30 DOWNTO 23),
        Op_A(31),Op_B(31),Exp1_2(7 DOWNTO 0),Exp1_2(8),RunO1_2);
        Ints_R1 : Divreg10 PORT MAP (Exp1_2, clk, reset, RunO1_2, Exp2_3, RunO2_3);
        Ints_R2 : Divreg10 PORT MAP (Exp2_3, clk, reset, RunO2_3, Exp3_4, RunO3_4);
        Ints_R3 : Divreg10 PORT MAP (Exp3_4, clk, reset, RunO3_4, Exp4_5, RunO4_5);
        Ints_R4 : Divreg10 PORT MAP (Exp4_5, clk, reset, RunO4_5, Exp5_6, RunO5_6);
        Ints_R5 : Divreg10 PORT MAP (Exp5_6, clk, reset, RunO5_6, Exp6_7, RunO6_7);
        Ints_R6 : Divreg10 PORT MAP (Exp6_7, clk, reset, RunO6_7, Exp7_8, RunO7_8);
	Ints_R7 : Divreg10 PORT MAP (Exp7_8, clk, reset, RunO7_8, Exp8_9, RunO8_9);
	Ints_R8 : Divreg10 PORT MAP (Exp8_9, clk, reset, RunO8_9, Exp9_10, RunO9_10);
        Ints_R9 : Divreg10 PORT MAP (Exp9_10, clk, reset, RunO9_10, Exp10_11, RunO10_11);
        Ints_R10 : Divreg10 PORT MAP (Exp10_11, clk, reset, RunO10_11, Exp11_12, RunO11_12);
        Ints_R11 : Divreg10 PORT MAP (Exp11_12, clk, reset, RunO11_12, Exp12_13, RunO12_13);
        Ints_R12 : Divreg10 PORT MAP (Exp12_13, clk, reset, RunO12_13, Exp13_14, RunO13_14);
        Ints_R13 : Divreg10 PORT MAP (Exp13_14, clk, reset, RunO13_14, Exp14_15, RunO14_15);
	Ints_R14 : Divreg10 PORT MAP (Exp14_15, clk, reset, RunO14_15, Exp15_16, RunO15_16);
        Op_A01(22 DOWNTO 0) <=Op_A(22 DOWNTO 0);
        Op_A01(23) <= '1';
        Op_B01(22 DOWNTO 0) <=Op_B(22 DOWNTO 0);
        Op_B01(23) <= '1';
        Inst_Div: pipelined_divider 
        generic map (30,24,15)
        port map (Op_A01,Op_B01,reset,clk,Result15_16);
        Inst_N1 : DivNorm1 PORT MAP (clk, reset, RunO15_16, Result15_16, Exp15_16, ZError, Op_Q, EnN);
		Inst_DB : DivideByZero PORT MAP (Op_B,Clk,Reset,Zerror);
END STRUCTURAL;