COURSE STUDY GUIDE

The following list is provided as a guide for preparing for the in class exams and the final exam for EECE 211.

Appendix A.

List for Appendix A:

Be familiar with positional notation for representing decimal, binary, octal and hexidecimal numbers.
Be able to convert between decimal, binary, octal or hexadecimal representations for numbers.
Be familiar with the concept of using successive division to change from base 10 (decimal) representations for numbers to base 2 (binary).
Be familiar with the general concept of addition in positional notation.
Be familiar with the general concept of subtraction in positional notation.

Chapter 5.

List for Chapter 5:

Be familiar with the representation of numbers using:
1. Sign and magnitude,
2. Twos complement.
Be able to add and subtract numbers represented in
1. Sign and magnitude,
2. Twos complement.
Be familiar with the overflow problem in adding and subtracting numbers and the procedure to detect overflow by comparing carry-in and carry-out.

Chapter 1.

List for Chapter 1:

Be familiar with representing logic functions using truth tables.
Be familiar with the Boolean operations such as AND, OR, NOT and be able to derive Boolean expressions from truth tables.
Be familiar with the correspondence between Boolean operations and logic gates and between Boolean expressions and gate networks.

Chapter 2.

List for Chapter 2:

Be familiar with the Axioms of Boolean Algebra
Be familiar with the different representations for Boolean operations such as NOT, OR, AND, NAND, NOR, XOR and XNOR.
Be familiar with the Laws and Theorems of Boolean Algebra and be able to use them to minimize Boolean expressions.
Be familiar with DeMorgan's Theorem and be able to use it to complement Boolean expressions involving several literals and/or several product terms or sum terms.
Be familiar with the expression canonical form and be able to obtain the canonical form for any given Boolean expression.
Be able to convert between the two canonical forms for Boolean expressions (SOP to POS or POS to SOP).
Be able to derive the SOP and the POS canonical expressions from any given Boolean expression.
Be able to simplify Boolean expressions having up to 5 variables using Karnaugh maps.
Be able to write an input file for use by espresso for a problem having up to 6 input variables and several outputs.

Chapter 3.

List for Chapter 3:

Be able to draw schematics for NAND-only networks from either AND-OR networks or Boolean expressions.
Be able to draw schematics for NOR-only networks from either AND-OR networks or Boolean expressions.
Be able to factor any given Boolean expression to obtain a multilevel logic implementation.
Be able to use misII to obtain a multilevel logic implementation of any given Boolean expression (See the example on in section 3.3.3 on page 129 of the text).
Be able to derive a two-level Boolean expression from any given multilevel Boolean expression and then find either the SOP or POS canonical form or the minimized two-level SOP or POS form.
Be able to derive a static hazard-free implementation from any specification of a Boolean function. The various specifications include truth table, K-map, unminimized SOP or POS form, canonical SOP or POS form, multilevel form, etc.

Chapter 4.

List for Chapter 4:

Be able to use a multiplexer to implement any given Boolean expression.
Be able to implement any Boolean expression using a two or three stage multiplexer.
Be able to implement any Boolean expression using a decoder and OR gates.
Be able to implement any Boolean expression using a ROM.

Chapter 6.

List for Chapter 6:

Be able to develop a state diagram from a word problem (See problem 6.2).
Be able to develop a state table from any given state diagram.
Be able to determine timing constraints on clocks, etc. for various feedback circuits from appropriate specifications for flip-flops and/or latches.
Be able to draw timing waveforms for clocks, inputs, outputs, etc. for various feedback circuits from appropriate specifications for flip-flops and/or latches.
Be familiar with methods for handshaking for asynchronous transfer of data.

Chapter 9.

List for Chapter 9:

Be able to use nova, mustang and jedi to investigate the most efficient state assignment for state machines with a few states (See section 9.3.4 on page 470 of the text).

Chapter 7.

List for Chapter 7:

Be familiar with the procedures for designing counters.
Be familiar with the concept of a counter being self-starting.
Be able to use data shifters to solve simple problems involving bit patterns.
Be able to develop Boolean expressions for inputs to any given type of flip-flops from a truth table providing the inputs, the present states and the next states. This requires using the state excitation table for the given flip-flop. (See Problem 7.12 ).

Chapter 8.

List for Chapter 8:

Be able to develop a state diagram from a word problem that describes a finite state machine or from a state table representation of a finite state machine.
Be able to develop a state table from a word problem that describes a finite state machine or from a state diagram representation of a finite state machine.