Department of Electrical and Computer Engineering
North Carolina State University

ECE 212 SPRING, 1994

FINAL EXAM - A
May 10, 1994

This is the final exam for ECE 212, Section 1 for Spring, 1994.

Instructions: This is an open book exam but you are not permitted to use notes. Put everything away except your pencil or pen and your text book for this course. Do all work on the test provided. If you need extra paper, raise your hand and extra paper will be provided. You can use the back of the pages for work space. However, make sure that your answers are placed in the space provided for each problem. Clearly indicate your answers. Also, put your name on the top of each page in the space provided for this purpose. If you desire to have your grade posted, then you must sign the following statement:

By my signature below, I give Dr. Winser Alexander permission to post my grade for ECE 212 or ECE 212S for Spring semester 1994 using my student number for identification.

 Signature:             (1,0)3

   

Print Name: 		 (1,0)3

   

Student Number: 		 (1,0)3

1. (Twos Complement Numbers) Perform the following additions or subtractions using twos complement arithmetic where the numbers are represented below in binary form (the most significant bit is the sign bit). In other words, perform the required operations using twos complement representations and addition only.

    a.

   000001  +  000100

    b.

   001111  -  000010

    c.

   001100  +  001010

    d.

   001011  -  001010

2. (Word Problem) A sequence detecting finite state machine has a single input X and two outputs, and . The output is asserted after each 7-bit input sequence if it is the string 1010011. The output is asserted if any other sequence occurs. You may assume that an external reset is provided after each 7-bit input sequence. Therefore, the machine can stay in the error state or the correct output state as appropriate until the reset has been provided. Develop a state table for this finite state machine.
3. (State Reduction) Given the state table below, obtain an equivalent reduced state table containing a minimum number of states. Make it clear which states have been combined.

    
   Table 1: State table for Problem 3.
   

4. (Word Problem) Implement a combinational logic circuit that converts a 4 bit sign plus magnitude number into the corresponding 4 bit twos complement number (the most significant bit is the sign bit).

   Complete the following truth table for the required functions:

    
   Table 2: Truth table for Problem 4.
   

    b.

   Minimize the output functions W, X, Y, and Z in sum of products form and write the minimized sum of products expressions below.

5. (Counter Design) The state table for a counter is given in Table 3. Implement this counter using T flip-flops.

    
   Table 3: State table for counter design in problem 5.
   

6. (Multilevel Logic) Factor the following sum of products expressions to show how they can be implemented as multilevel circuits.

    a.

    b.

7. (Multiplexer Logic) Implement the following function (not necessarily minimized) using an 8:1 multiplexer using A, B, and C as the selection inputs:

8. (ROM-Based Implementation) Show how to implement the following functions using a 16 word by 4 bit ROM.

• About this document ...